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NS公司的ADC12D1800是超高速(3.6GSPS)12位模数转换器,提供灵活的LVDS接口,有多个可编程的SPI选择,利于板的设计和FPGA/ASIC数据采集,LVDS输出和IEEE 1596.3-1996兼容,单电源,噪音平面-149.5 dBm/Hz,IMD3为-61dBFS,噪音功率比为48.5dB,典型功耗为4.4W,主要用在宽带通信,雷达/LIDAR,机顶盒,工业控制和数据采集系统以及软件定义无线电(SDR).本文介绍了ADC12D1800主要特性和指标, 简化方框图以及ADC12D1X00RB演示板方框图,电路图和所用材料清单(BOM).NS公司的ADC12D1800是超高速(3.6GSPS)12位模数转换器,提供灵活的LVDS接口,有多个可编程的SPI选择,利于板的设计和FPGA/ASIC数据采集,LVDS输出和IEEE 1596.3-1996兼容,单电源,噪音平面-149.5 dBm/Hz,IMD3为-61dBFS,噪音功率比为48.5dB,典型功耗为4.4W,主要用在宽带通信,雷达/LIDAR,机顶盒,工业控制和数据采集系统以及软件定义无线电(SDR).本文介绍了ADC12D1800主要特性和指标, 简化方框图以及ADC12D1X00RB演示板方框图,电路图和所用材料清单(BOM).NS公司的ADC12D1800是超高速(3.6GSPS)12位模数转换器,提供灵活的LVDS接口,有多个可编程的SPI选择,利于板的设计和FPGA/ASIC数据采集,LVDS输出和IEEE 1596.3-1996兼容,单电源,噪音平面-149.5 dBm/Hz,IMD3为-61dBFS,噪音功率比为48.5dB,典型功耗为4.4W,主要用在宽带通信,雷达/LIDAR,机顶盒,工业控制和数据采集系统以及软件定义无线电(SDR).本文介绍了ADC12D1800主要特性和指标, 简化方框图以及ADC12D1X00RB演示板方框图,电路图和所用材料清单(BOM).
The 12-bit, 3.6 GSPS ADC12D1800 is the latest advance in National’s Ultra-High-Speed ADC family and builds upon the features, architecture and functionality of the 10-bit GHz family of ADCs.
The ADC12D1800 provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage.
The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40℃ to +85℃.
ADC12D1800主要特性:
■ Configurable to either 3.6 GSPS interleaved or 1.8 GSPS dual ADC
■ Pin-compatible with ADC10D1000/1500 and ADC12D1000/1600
■ Internally terminated, buffered, differential analog inputs
■ Interleaved timing automatic and manual skew adjust
■ Test patterns at output for system debug
■ Programmable 15-bit gain and 12-bit plus sign offset
■ Programmable tAD adjust feature
■ 1:1 non-demuxed or 1:2 demuxed LVDS outputs
■ AutoSync feature for multi-chip systems
■ Single 1.9V ± 0.1V power supply
ADC12D1800主要指标:
■ Resolution 12 Bits Interleaved 3.6 GSPS ADC
■ Noise Floor -149.5 dBm/Hz (typ)
■ IMD3 -61 dBFS (typ)
■ Noise Power Ratio 48.5 dB (typ)
■ Power 4.4W (typ)
■ Full Power Bandwidth 1.75 GHz (typ) Dual 1.8 GSPS ADC, Fin = 125MHz
■ ENOB 9.4 (typ)
■ SNR 58.5 dB (typ)
■ SFDR 73 dBc (typ)
■ Power 4.4W (typ)
■ Full Power Bandwidth 2.8 GHz (typ)
ADC12D1800应用:
■ Wideband Communications
■ Data Acquisition Systems
■ RADAR/LIDAR
■ Set-top Box
■ Consumer RF
■ Software Defined Radio
图1.ADC12D1800简化方框图
ADC12D1X00RB参考板
图2.ADC12D1X00RB参考板外形图
The ADC12D1X00RB demonstrates a high-performance signal acquisition sub-system that achieves 12-bit resolution and corresponding SNR and dynamic range on two channels at signal frequencies in excess of 1.0 GHz and sampling rates of at least 1.0/1.6/1.8 GS/s or one channel at a sampling rate of 2.0/3.2/3.6 GHz. The board showcases the following National Semiconductor devices:
• ADC12D1X00 analog-to-digital converter
• LMX2531 clock synthesizer
• LP3878MR-ADJ/NOPBLP3878MR-ADJ/NOPB and LP38853S-ADJ/NOPBLP38853S-ADJ/NOPB linear LDO regulators
• LM20242, LM25576EVALLM25576EVAL and LM26400YMH/NOPBLM26400YMH/NOPB switching regulators
• LM3880 power sequencing controller
• LM95233 temperature sensor
In addition, the board also employs the Xilinx XC4VLX25-11FFG668 Virtex-4 FPGA for the critical function of capturing the high-speed digital data sourced by the ADC.
ADC12D1X00RB参考板主要特性:
Demonstrates the ADC12D1X00’s typical dynamic performance – see the datasheet for
full details.
Sample rates of up to 1.0/1.6/1.8 GS/s (limited by the ADC specifications and the FPGA
capture limitations)
Input signal frequencies up to 2.8 GHz (Non-DES Mode Full-Power Bandwidth)
On-board LMX2531 based clock circuit with a connector for a selectable external clock
A complete high-performance low-noise power management section for the ADC, clock circuit, FPGA and USB controller
Single +7.5V power adapter input
Simplicity and performance of USB 2.0 connection to the PC
Functions with National’s latest WaveVision 5 signal-path control and analysis software.
图3.ADC12D1X00RB系统方框图
图4.ADC12D1X00RB参考板电路图(1)
图5.ADC12D1X00RB参考板电路图(2)
图6.ADC12D1X00RB参考板电路图(3)
图7.ADC12D1X00RB参考板电路图(4)
图8.ADC12D1X00RB参考板电路图(5)
图9.ADC12D1X00RB参考板电路图(6)
图10.ADC12D1X00RB参考板电路图(7)
图11.ADC12D1X00RB参考板电路图(8)
图12.ADC12D1X00RB参考板电路图(9)
图13.ADC12D1X00RB参考板电路图(10)
图14.ADC12D1X00RB参考板电路图(11)
The 12-bit, 3.6 GSPS ADC12D1800 is the latest advance in National’s Ultra-High-Speed ADC family and builds upon the features, architecture and functionality of the 10-bit GHz family of ADCs.
The ADC12D1800 provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage.
The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40℃ to +85℃.
ADC12D1800主要特性:
■ Configurable to either 3.6 GSPS interleaved or 1.8 GSPS dual ADC
■ Pin-compatible with ADC10D1000/1500 and ADC12D1000/1600
■ Internally terminated, buffered, differential analog inputs
■ Interleaved timing automatic and manual skew adjust
■ Test patterns at output for system debug
■ Programmable 15-bit gain and 12-bit plus sign offset
■ Programmable tAD adjust feature
■ 1:1 non-demuxed or 1:2 demuxed LVDS outputs
■ AutoSync feature for multi-chip systems
■ Single 1.9V ± 0.1V power supply
ADC12D1800主要指标:
■ Resolution 12 Bits Interleaved 3.6 GSPS ADC
■ Noise Floor -149.5 dBm/Hz (typ)
■ IMD3 -61 dBFS (typ)
■ Noise Power Ratio 48.5 dB (typ)
■ Power 4.4W (typ)
■ Full Power Bandwidth 1.75 GHz (typ) Dual 1.8 GSPS ADC, Fin = 125MHz
■ ENOB 9.4 (typ)
■ SNR 58.5 dB (typ)
■ SFDR 73 dBc (typ)
■ Power 4.4W (typ)
■ Full Power Bandwidth 2.8 GHz (typ)
ADC12D1800应用:
■ Wideband Communications
■ Data Acquisition Systems
■ RADAR/LIDAR
■ Set-top Box
■ Consumer RF
■ Software Defined Radio
图1.ADC12D1800简化方框图
ADC12D1X00RB参考板
图2.ADC12D1X00RB参考板外形图
The ADC12D1X00RB demonstrates a high-performance signal acquisition sub-system that achieves 12-bit resolution and corresponding SNR and dynamic range on two channels at signal frequencies in excess of 1.0 GHz and sampling rates of at least 1.0/1.6/1.8 GS/s or one channel at a sampling rate of 2.0/3.2/3.6 GHz. The board showcases the following National Semiconductor devices:
• ADC12D1X00 analog-to-digital converter
• LMX2531 clock synthesizer
• LP3878MR-ADJ/NOPBLP3878MR-ADJ/NOPB and LP38853S-ADJ/NOPBLP38853S-ADJ/NOPB linear LDO regulators
• LM20242, LM25576EVALLM25576EVAL and LM26400YMH/NOPBLM26400YMH/NOPB switching regulators
• LM3880 power sequencing controller
• LM95233 temperature sensor
In addition, the board also employs the Xilinx XC4VLX25-11FFG668 Virtex-4 FPGA for the critical function of capturing the high-speed digital data sourced by the ADC.
ADC12D1X00RB参考板主要特性:
Demonstrates the ADC12D1X00’s typical dynamic performance – see the datasheet for
full details.
Sample rates of up to 1.0/1.6/1.8 GS/s (limited by the ADC specifications and the FPGA
capture limitations)
Input signal frequencies up to 2.8 GHz (Non-DES Mode Full-Power Bandwidth)
On-board LMX2531 based clock circuit with a connector for a selectable external clock
A complete high-performance low-noise power management section for the ADC, clock circuit, FPGA and USB controller
Single +7.5V power adapter input
Simplicity and performance of USB 2.0 connection to the PC
Functions with National’s latest WaveVision 5 signal-path control and analysis software.
图3.ADC12D1X00RB系统方框图
图4.ADC12D1X00RB参考板电路图(1)
图5.ADC12D1X00RB参考板电路图(2)
图6.ADC12D1X00RB参考板电路图(3)
图7.ADC12D1X00RB参考板电路图(4)
图8.ADC12D1X00RB参考板电路图(5)
图9.ADC12D1X00RB参考板电路图(6)
图10.ADC12D1X00RB参考板电路图(7)
图11.ADC12D1X00RB参考板电路图(8)
图12.ADC12D1X00RB参考板电路图(9)
图13.ADC12D1X00RB参考板电路图(10)
图14.ADC12D1X00RB参考板电路图(11)
The 12-bit, 3.6 GSPS ADC12D1800 is the latest advance in National’s Ultra-High-Speed ADC family and builds upon the features, architecture and functionality of the 10-bit GHz family of ADCs.
The ADC12D1800 provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage.
The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40℃ to +85℃.
ADC12D1800主要特性:
■ Configurable to either 3.6 GSPS interleaved or 1.8 GSPS dual ADC
■ Pin-compatible with ADC10D1000/1500 and ADC12D1000/1600
■ Internally terminated, buffered, differential analog inputs
■ Interleaved timing automatic and manual skew adjust
■ Test patterns at output for system debug
■ Programmable 15-bit gain and 12-bit plus sign offset
■ Programmable tAD adjust feature
■ 1:1 non-demuxed or 1:2 demuxed LVDS outputs
■ AutoSync feature for multi-chip systems
■ Single 1.9V ± 0.1V power supply
ADC12D1800主要指标:
■ Resolution 12 Bits Interleaved 3.6 GSPS ADC
■ Noise Floor -149.5 dBm/Hz (typ)
■ IMD3 -61 dBFS (typ)
■ Noise Power Ratio 48.5 dB (typ)
■ Power 4.4W (typ)
■ Full Power Bandwidth 1.75 GHz (typ) Dual 1.8 GSPS ADC, Fin = 125MHz
■ ENOB 9.4 (typ)
■ SNR 58.5 dB (typ)
■ SFDR 73 dBc (typ)
■ Power 4.4W (typ)
■ Full Power Bandwidth 2.8 GHz (typ)
ADC12D1800应用:
■ Wideband Communications
■ Data Acquisition Systems
■ RADAR/LIDAR
■ Set-top Box
■ Consumer RF
■ Software Defined Radio
图1.ADC12D1800简化方框图
ADC12D1X00RB参考板
图2.ADC12D1X00RB参考板外形图
The ADC12D1X00RB demonstrates a high-performance signal acquisition sub-system that achieves 12-bit resolution and corresponding SNR and dynamic range on two channels at signal frequencies in excess of 1.0 GHz and sampling rates of at least 1.0/1.6/1.8 GS/s or one channel at a sampling rate of 2.0/3.2/3.6 GHz. The board showcases the following National Semiconductor devices:
• ADC12D1X00 analog-to-digital converter
• LMX2531 clock synthesizer
• LP3878MR-ADJ/NOPBLP3878MR-ADJ/NOPB and LP38853S-ADJ/NOPBLP38853S-ADJ/NOPB linear LDO regulators
• LM20242, LM25576EVALLM25576EVAL and LM26400YMH/NOPBLM26400YMH/NOPB switching regulators
• LM3880 power sequencing controller
• LM95233 temperature sensor
In addition, the board also employs the Xilinx XC4VLX25-11FFG668 Virtex-4 FPGA for the critical function of capturing the high-speed digital data sourced by the ADC.
ADC12D1X00RB参考板主要特性:
Demonstrates the ADC12D1X00’s typical dynamic performance – see the datasheet for
full details.
Sample rates of up to 1.0/1.6/1.8 GS/s (limited by the ADC specifications and the FPGA
capture limitations)
Input signal frequencies up to 2.8 GHz (Non-DES Mode Full-Power Bandwidth)
On-board LMX2531 based clock circuit with a connector for a selectable external clock
A complete high-performance low-noise power management section for the ADC, clock circuit, FPGA and USB controller
Single +7.5V power adapter input
Simplicity and performance of USB 2.0 connection to the PC
Functions with National’s latest WaveVision 5 signal-path control and analysis software.
图3.ADC12D1X00RB系统方框图
图4.ADC12D1X00RB参考板电路图(1)
图5.ADC12D1X00RB参考板电路图(2)
图6.ADC12D1X00RB参考板电路图(3)
图7.ADC12D1X00RB参考板电路图(4)
图8.ADC12D1X00RB参考板电路图(5)
图9.ADC12D1X00RB参考板电路图(6)
图10.ADC12D1X00RB参考板电路图(7)
图11.ADC12D1X00RB参考板电路图(8)
图12.ADC12D1X00RB参考板电路图(9)
图13.ADC12D1X00RB参考板电路图(10)
图14.ADC12D1X00RB参考板电路图(11)