Note: The information here describes how a Vector Network Analyzer (VNA) can internally function. To first find out what measurements a VNA can perform as a black box connected to a device-under-test (DUT), see HF Vector Network Analyzer - Some Measurement Examples

The design described here is known as the N2PK VNA implementation. Other VNAs work differently internally. The information is useful for those interested in constructing and working with the N2PK VNA, but is also useful to all VNA users, since an understanding of how a VNA could function accelerates ones understanding of how to use any VNA. To that end, there are links further below to commercial VNA instruments and manufacturer notes as well.

This document's copyright belongs to Paul Kiciak, N2PK, pkiciak@adelphia.net, reproduced with his permission.

Any minor changes are for converting to HTML content with page jumps or splitting content, adding hyperlinks and so on - i.e. purely readability related. Any word modifications more significant than that will always be indicated in some manner (e.g. highlighting or notes), so that the original text meaning or data is not lost. This document is also under version control. All diagrams/photos are clickable to increase the resolution. If you have any corrections or comments, or or information to contribute, please comment below (it is possible to insert high-res inline photos/diagrams and videos in the comments below too).

Introduction

There is much information related to general vector network analyzer principles available on the web. See these four papers and six other papers that can be searched on the Keysight website:

• Understanding the Fundamental Principles of Vector Network Analysis
• Exploring the Architectures of Network Analyzers
• Applying Error Correction to Vector Network Analyzer Measurements
• Network Analyzer Measurements: Filter and Amplifier Examples

In particular, the second paper listed above describes the typical VNA architectures. The referenced documents will be assumed as a base for what follows.

The key elements of a typical VNA are:

• A synthesized signal source that is voltage and/or software controlled.
• Couplers or bridges to separate incident from reflected signals.
• One or more receivers or detectors capable of amplitude and phase detection.
• Controls, data collection, and processing
• The Device Under Test (DUT), which can be a one-port or multi-port device
• Calibration (Reference and Calibration Planes)

The phase detection feature of the receiver or detector is what distinguishes a VNA from a scalar network analyzer (SNA). One example of an SNA is a spectrum analyzer with a tracking generator.

These elements of a VNA will be considered in further detail with reference to the block diagram shown on Figure 16 below. This diagram shows the essential elements of the printed circuit board (PCB) to be described in a later section. One salient feature in Figure 16 is that there are no hardware calibration at a single frequency adjustments in this VNA.

How it Works – An Overview

Imagine a simple transmission measurement through a DUT (See Fig 16 N2PK VNA Block Diagram below). The RF DDS generates an RF voltage at the reference phase of 0 deg, and this signal is applied to the input of the DUT. The output from the DUT to the Detector input is an RF signal with amplitude |V_RF| at a phase φ_RF. In addition, the RF signal at the Detector input is measured with a ‘Through’ in place of the DUT. The ’Through’ is simply a short length of transmission line that is assumed to have unity gain and zero phase. The Detector output is also measured without any intentional RF signal at the Detector input. This test condition is referred to as the ‘Open Detector.’ For test flow reasons, the ‘Through’ and the ‘Open Detector’ measurements are made before the DUT is inserted and measured.

From these three vector measurements at a single frequency, all DUT transmission characteristics, such as gain and phase, can be calculated. Group delay requires two or more frequencies.

Similarly, all impedance characteristics of the DUT can be measured at each frequency of interest using a standard Wheatstone type reflection bridge. Here, the DUT |V_RF| and φ_RF are measured relative to three precision terminations. The terminations are typically an open, a short, and one that approximates the system reference impedance (usually 50 Ω). These three calibration standards also allow the use of other measurement fixtures (not strictly bridges) that provide improved accuracy for high or low DUT impedances - see later.

|V_RF| is quite easy to measure, but there are several different ways to determine the relative phase information θ_RF.

Most lab-quality VNAs use a superhet architecture that converts both the reference signal and the detected signal to a fixed IF for precision amplitude and phase detection. These conversions occur via conventional mixing or sampling. This architecture, as normally implemented, is complex and expensive.

A much simpler architecture is used in the recent ‘VNA on a chip’ device - the Analog Devices AD8302, with its broadband logarithmic detection of amplitude information and high-speed logic for the phase comparison. The disadvantage here is considerably reduced accuracy compared to a lab-quality VNA.

This VNA is different – it uses a narrow-band direct-conversion architecture that is much simpler than superhet VNAs, but is also much more accurate than the log-detection devices. Because the Detector in this VNA converts down to DC, the only output available is a DC voltage, which isdependent not only on the magnitude of the RF voltage at its input, but also its phase relative to the RF signal at its LO input. Highly accurate measurements of this amplitude and phase dependent DC voltage are obtained using a precision linear analog detector, a 24-bit analog-digital converter (ADC), and precise phase control of the LO DDS.

The phase information is obtained, in a novel way, by making two sequential DC measurements for each frequency and test condition (Through, Open Detector, and DUT). In each case, the first measurement is made with the LO at the reference phase of 0 deg; the second measurement is made with the LO phase shifted by 90 deg. This process results in the quadrature or vector components of each signal at the Detector RF input.

The result is a very simple hardware architecture, which takes maximum advantage of modern developments: the ability of a computer-controlled DDS to generate precise frequencies and phase shifts; precision 24-bit analog-to-digital conversion; and the power of computer control and post-processing. The computer processing completely eliminates setup adjustments, and allows many common sources of measurement errors to be ‘calibrated out’. This greatly simplifies home construction.

Signal Source

There are two signal sources in this VNA. Both are based on direct digital synthesis (DDS). This reference supplies the general concepts of DDS technology and is assumed for what follows.

The RF DDS provides the signal source to the bridge and DUT during reflection measurements, or directly to the DUT for transmission measurements. The output from either the bridge or the 2nd port on the Device Under Test (DUT) feeds the RF input of the Detector.

The Detector is a balanced mixer (see later) and the LO DDS provides the reference phase signal to the LO input of the Detector.

In normal VNA operation, the LO DDS is frequency and phase synchronized with the RF DDS. Both DDSs operate at the same frequency, which nominally ranges from 50 kHz to 60 MHz with a minimum frequency step size of approx. 0.035 Hz. In addition, both are usable for non-VNA applications below 50 kHz, particularly the LO DDS which is not transformer  coupled.

Each DDS can be phase programmed from 0 to 360 degrees in 11.25 degree increments. As seen in Figure 13, the RF DDS is always programmed for 0 degrees while the LO DDS is programmed for either 0 or 90 degrees in typical VNA usage. The motivation for these phase selections will be described in the Detector section.

A 148.34 MHz crystal oscillator provides the master oscillator for the DDSs. This oscillator also synchronizes the frequency update control line from the PC to ensure that the desired relative phase is maintained between the RF and the LO DDSs. The original intent in this VNA was to support the 6X mode in the DDS to permit the use of a master oscillator at a lower frequency, which would have been easier to implement. When in 6X mode, a PLL internal to each DDS is enabled to permit a 6X frequency multiplication and synchronization at about 147.5 MHz, with only a 24.6 MHz master oscillator as input. However, three problems arose. The first was that amplitude and phase jitter was higher at certain frequencies with the DDS PLLs enabled. As a result, VNA measurement accuracy suffers, particularly near 24.6 MHz where the programmed frequency is within a few tuning words of 2AAAAAAAh, or about the internal master oscillator frequency divided by six. The second was that recently available Analog Devices DDS chip notes indicate that both modes cannot be easily supported by one hardware configuration. This explains the intermittent software difficulties noted while attempting to operate in 6X mode with hardware designed for 1X mode. The third was that support of both modes was becoming increasingly difficult, as more software was being written and requiring test. As a result, support of the 6X mode was dropped in favor of a stable, low-noise crystal oscillator that generates 148.34 MHz directly.

Even with the DDS PLLs disabled, there is increased amplitude and phase jitter at certain frequencies with the largest increase near the 55555555h tuning word, which corresponds to the master oscillator frequency divided by three, or about 49.45 MHz. The jitter increases are caused primarily by an inverted alias that is in the Detector bandwidth, about –45 dBc, and modulates the detected amplitude. While these largest jitters amount to about a worst-case +/-0.2 dB uncertainty in transmission magnitude, or about +/-1.0 degree uncertainty in phase, and both are small for some purposes, the master oscillator frequency is selected so that jitter increases do not occur at ‘round’ number frequencies.

Anti-alias filters are provided on each primary DDS output to reduce the spurious DDS outputs above the Nyquist frequency. These filters start rolling off at about 50 MHz.

All DDS outputs are nominally reverse terminated in 50Ω, over a frequency range defined by AC coupling at the low end and an anti-alias filter, where present, at the high end. External 50 Ω attenuators (pads) can be used to improve source match at the expense of dynamic range.

To permit other uses of the VNA hardware, the DDS controls were configured to allow independent frequencycontrol of each DDS. The auxiliary LO DDS output was not provided with an anti-alias filter to conserve board space and also since this output is not required for primary VNA functions. However, one can be easily added externally to support other uses, if desired.

Most commercial VNAs provide RF output level control. In the interest of simplicity, that feature was not provided here and can be readily supplied externally as needed with an attenuator.

Couplers and Bridges

There is a wide variety of devices that can be used here, but the requirement is always the same – to provide a measure of the signal reflected from a port on the DUT. A sampling of devices that can be used is:

• Return loss bridge (see The ARRL Handbook, 78th Edition(2001), p. 26.42, Fig C).
• Two-way power splitter such as the Mini-Circuits PSC2-1 or the PSC-2-1W
• Directional coupler such as the Mini-Circuits PDC-10-1
• Two transformer directional coupler (see notes at the end of this document)

Bridges with high output impedances, such as the Bruene bridge, are typically not suited for VNA use, due to the VNA 50 Ω impedances.

For each of these devices, there are differences from the ideal for measures of the reflected signal. In all cases, however, the OSL calibration described below accounts for most sources of error.

While not generally considered a bridge, even something as simple as a 3-way tee connector directly connecting the RF DDS, the Detector RF input, and the DUT can be used. Unlike the conventional return loss bridge, this bridge is nominally ‘balanced’ when a short is placed on the DUT port, since the DUT shunts the RF DDS signal to ground so that little is available for detection.

Since this bridge is designed to make optimum use of the VNA’s dynamic range for low DUT impedances, in Part 2 it is referred to as the “Low-Z” bridge. It is best suited for unbalanced DUTs, but the addition of a transformer can be useful for low impedance balanced DUTs, such as a loop antenna.

In similar fashion, the DUT can be inserted in series between the RF DDS and the Detector RF Input. This ‘bridge’ is balanced when an open is placed on the DUT port, since this DUT provides little signal for detection. In Part 2, this bridge is referred to as the High-Z bridge. This bridge is best used for measurements on physically small components since both DUT terminals are above RF ground, although a suitable transformer might be useful for unbalanced or balanced DUTs.

By AC coupling the RF DDS and DUT ports and DC coupling the DUT port and adding a bias resistor at the junction to a DC power supply, a simple Low-Z bridge can be built that allows testing of some active DUTs or bias dependent passive ones. This is much simpler, in most cases, than modifying one of the devices in the list above to accept DC biasing.

The combination of a Wheatstone type return loss bridge, the Low-Z bridge, and the High-Z bridge, with modifications as needed for DC biasing, can provide highly accurate measurements over a wide range of impedances.

Detector

This VNA utilizes a single Detector for both vector components of the RF input signal. It is a somewhat conventional linearized Gilbert-cell product detector (mixer) with a twist. Where a product detector is frequently provide with an LO (BFO) that is asynchronous with its RF signal and the information is contained in the detected sidebands, this product detector uses a synchronous LO and the desired information is in the detected carrier. Since the intermediate frequency (IF) in this case is zero Hz, the DC voltage at the Detector output contains the desired carrier information. This can be seen from Equation 1 that describes the Detector output voltage, V_DC:

where, at each frequency,

|G_DET| is the magnitude of the Detector gain,

|V_RF| is the magnitude of the voltage at the Detector RF input,

φ_RF is the phase at the Detector RF input,

φ_LO is the phase at the Detector LO input,

θ_DET is the phase constant related to Detector gain and,

V_off is an offset voltage with no applied signal at the RF input.

The absolute phase values for φ_RF and φ_LO are arbitrary since the reference for time is not specified. So, let’s assume here that φ_LO can be programmed to values of 0 and 90 degrees at different times. As a result, the Detector output takes on two DC values that together represent the quadrature or vector components of the applied RF signal within a vector constant, as shown in Equations 2 and 3.

The vector-offset voltage is obtained by measuring VDC when V_RF is zero, i.e. with no input to the Detector. Its use in the computations is described below.

The LO DDS is connected to the Detector LO input in balanced fashion to minimize coupling back to the RF input, which is also balanced. The LO level is deliberately chosen to overdrive the Detector input, which makes its amplitude a second order effect that is accounted for principally in |G_DET|, θ_DET, and V_off.

To illustrate the application of equations 2 and 3 in this VNA, consider again the DUT transmission measurement.

At each test frequency and for each of the Through, Open Detector, and DUT test conditions:

1. Apply V_LO at the reference phase 0 deg, and measure V_DC,0 (equation 2)
2. Apply V_LO at the a phase of 90 deg, and measure V_DC,90 (equation 3)

The vector DC offset voltage, with components V_OFF,0 and V_OFF,90, is obtained from the Open Detector calibration, which is considered to result in |V_RF| = 0. The computer subtracts these values from all subsequent measurements.

With V_OFF,0 and V_OFF,90 known, the constants G_DET and θ_DET in equations 2 and 3 are then implicitly determined with the ‘Through’ calibration. In actual fact, the measured values are converted to complex numbers to simplify the manipulations.

After the DUT measurement, standard complex number arithmetic is used to obtain the complex DUT gain, G_DUT, in terms of the six measured Detector values expressed as three complex numbers:

From G_DUT, expressions of magnitude as a real number and dB and phase in degrees are obtained. Group delay is determined from delta(θ_DUT)/delta(f) using data at two frequencies.

Once collected, the Through and Open Detector calibration measurements can be used for subsequent DUTs as well.

A similar procedure is followed for reflection measurements using three calibration standards and the DUT. In this case, a separate no-signal measurement is not required to establish the Detector offset.

This method of vector detection is what I call sequential quadrature to distinguish it from the simultaneous quadrature done in other VNAs and real-time I/Q demodulators that employ two detectors and quadrature LOs instead.

While sequential quadrature is slower in terms of data collection, there are accuracy advantages due to gain and phase calibration tracking that results from the use of one detector and one LO that can be precisely phase shifted by 90 degrees. Note also that, in this configuration, absolute relative phase between the RF and LO DDSs is not at all important. Only the ability to precisely phase shift one DDS is critical to accuracy.

To further enhance accuracy, the detector DC output is processed as a differential signal, through to the differential input of the ADC. This provides valuable rejection of commonmode errors caused by thermal effects, power supply variation, and stray AC fields.

The Detector output is analog low pass filtered with a 3 dB cut-off at about 100 Hz (baseband). This filter is present to augment the ADC’s Sinc digital filter, which has its 1st 3 dB down point at about 3.6 Hz. But the digital filter doesn’t roll-off monotonically and has several large peaks at multiples of 15 Hz and at multiples of the 15,360 Hz sampling frequency (60 Hz notch frequency). For a 50 Hz notch frequency, these would change to 12.5 Hz and 12,800 Hz respectively. The analog filter time constant was selected to ensure that the Detector output settling time (about 14.5 filter time constants for 1 ppm) does not significantly increase the overall conversion time.

The analog filter output is also buffered by a pair of low offset, low drift, op amps to present an appropriate differential source impedance to the ADC.

The ADC is a differential input delta-sigma type with an integrated oscillator. The external voltage reference is differential to the ADC as well. ADC conversion time is relatively long at 130 ms, but that is the price paid here to obtain dynamic range on the order of 110-120 dB.

Based on measurements with an offset frequency on the RF DDS, the equivalent RF bandwidth of this Detector is about 5 Hz. So this Detector indeed qualifies as narrowband.

The return loss with respect to 50 Ω on the Detector RF input exceeds 30 dB over the HF range.

Since the data collected is vector in nature, averaging can be used to reduce the effective noise floor or effects of nonsynchronous signals. While still subject to ultimate accuracy limitations due to drift, averaging can be helpful in some cases and the software allows the user to select the degree of averaging to be used.

Harmonic Mixing

One consequence of direct conversion and an over-driven LO Detector input is the potential for harmonic mixing. That can be used to advantage as one way to extend the frequency range of the instrument, but it can also result in undesired spurious responses. In particular, the 3rd harmonic can result in significant responses that may be either desirable or not. Desirable harmonic mixing may be considered in a later part, but for now, we will consider the general mechanism and its effect on undesired responses.

For example, consider a filter designed for low insertion loss around its passband center frequency, Fc. Due to the over-driven Detector LO input, RF DDS harmonics, and potential harmonic generation within the DUT, a spurious response centered on Fc/3 will occur. That response can be about 80-90 dB down from the main filter passband response,

neglecting the DUT contribution, and even higher if the DUT is a significant harmonic generator.

This is the result of the 3rd harmonic of the RF DDS passing through the filter passband essentially un-attenuated and mixing with the 3rd harmonic of the DDS LO. Due to the overdriven Detector LO input, 3rd harmonic mixing is only about 11 dB less efficient than fundamental mixing.

If the filter’s response near Fc/3 is 60 dB down from the passband response, then the spurious response due to harmonic mixing will have a negligible effect. However, if the filter response is 100 dB down at Fc/3, then the spurious response will be seen as miniature passbands 1/3 as wide and centered on Fc/3.

If a suspicious response is seen, then an attenuator can be added to either the RF or LO DDS path to aid in determining its location.

If known attenuation between the RF DDS and the DUT results in higher relative measured attenuation at some frequencies, then this can be due to harmonic generation in the DUT. In this case, attenuation must be added until the desired linear response is obtained. This test only points to the DUT if the VNA Detector RF Input is not over-driven under any test condition.

Alternatively, adding an optional 20 dB attenuator between the LO DDS and the Detector LO input, as shown in Figure 16, will significantly reduce harmonic mixing. If a suspicious response is reduced in relative amplitude, then a VNA spurious response is indicated. While the spurious response can be reduced by over 25 dB to over 100 dB overall or better, there is a loss in dynamic range that is not generally desirable. This may be dealt with in further detail in a future post.

While a superhet approach in place of direct conversion would essentially eliminate the effects of harmonics (desired and undesired), a superhet would still be vulnerable to DDS aliases and now their other spurious outputs at frequencies more difficult to predict than the harmonics. A superhet and DDS clean-up using PLLs would result in a significant increase in hardware complexity with only a minor improvement in measurement accuracy in most cases.

Controls, Data Collection, Processing

Control over this VNA hardware is established via an interface to the parallel port on an IBM compatible personal computer (PC). The hardware does nothing without the PC and powers up “dumb.” In fact, warm-up of the unit doesn’t really start until one of the PC test programs has been started and the DDSs have been programmed to some representative frequency to be tested later after warm-up is complete.

The bus interface provides for ESD protection, has receivers with hysteresis for noise immunity, and has drivers capable of handling parallel port cables and loads per the IEEE 1284 standard.

The hardware is controlled by PC test programs which also collect the data from the ADC and perform subsequent data reductions to a variety of useful parameters. Several programs allow for stepping over a frequency range (spot, log, and linear), on-screen presentation of the reduced data after all collection is complete, and also data storage in a file. Other programs offer a quasi real-time capability at a single frequency with an on-screen and continuously updated display of the reduced data.

Device Under Test (DUT)

The Device Under Test (DUT) can be virtually any one, two, or multi-port network for which a linear characterization is useful. Care must be taken with some DUTs to avoid overdriving them and/or the VNA Detector. As noted above, an external attenuator can be used at the RF DDS to limit the drive to an acceptable level. In appropriate cases, the RF DDS output may also be amplified, but always subject to a maximum usable input of +5.5 dBm into the Detector as noted in the Performance Summary article.

Calibration

An integral concept of any VNA is the reference plane (see this Keysight PDF for a description of the Reference Plane and the Calibration Plane). For reflection measurements, the reference plane is the location on each DUT port where impedance is defined and is essentially defined by the location of the calibration standards and the DUT as shown on Figure 17. In addition, the calibration plane is also defined, normally somewhere in the junction between the two halves of mating RF connectors.

One predominant usage of this VNA has been the precise characterization of components that are not associated with some particular connector system. Hence it is not particularly useful for the connector to be part of the DUT, particularly when the component impedances are much greater or less than 50 Ω. As a result, reflection data collected with this VNA currently are with respect to the reference plane.

For impedances thru 30 MHz with relatively low VSWR that are of interest at some particular connector interface, the differences between the impedances at the two plane locations are frequently negligible. However, for more demanding applications, the differences can be significant. At some time in the future, a choice may be offered to the user to define which plane is of interest for a particular measurement. This will also require of the definition of the parameters of the transmission line, normally its Zo and electrical length T, as shown in Figure 17. These parameters, which clearly also depend on the connector system used during calibration, introduce an additional level of complexity.

For transmission measurements of two or multi-port networks, the calibration plane locations for each port are individually defined as shown in Figure 18. The Thru line lies between the two calibration planes and thru 60 MHz would normally be characterized by Zo and an electrical length T (i.e. ignore loss). However, thru line parameters currently are assumed to be negligible since even something as large as an SO-239 to SO-239 barrel would result in only about 1.3 degrees of phase error at 30 MHz and about 1.8 degrees for an SMA-SMA barrel at 60 MHz. Again, this type of calibration refinement may be made in the future, but will require additional complexity and attention to detail by the user.

This VNA lends itself to a full Open, Short, and Load (OSL) calibration for reflection measurements and a modified Response calibration for transmission measurements. These calibrations are normally performed after warm-up, and immediately prior to measurement of the DUT.

OSL calibration basically views the entire VNA in reflection mode, from the reference plane to the ADC output as read by the PC software, as a linear two-port network. As such, this calibration accounts for what is normally termed systematic errors. Random, drift, and non-linear errors are not accounted for. The combination of drift and desired measurement accuracy normally determines how often calibration must be performed.

While four parameters generally characterize a two-port network, only three are required in this case since a numerical value for the product of two parameters is sufficient as shown in Eq. 4.

Hence, only three known loads are required to establish numerical values for E₁₁, E₂₁xE₁₂, and E₁₂ at each test frequency. Armed with values for measured reflection coefficient, ρ_meas, E₁₁, E₂₁xE₁₂, and E₁₂, Eq. 4 can be used to solve for an estimate of the actual DUT reflection coefficient, ρ_DUT.

Conventional VNA Response calibration, used during transmission measurement of two or multi-port networks, requires a thru transmission line to establish a complex reference value at each test frequency for unity transmission in an assumed 50 Ω system. The Modified Response calibration employed in this VNA also accounts for the frequency-dependent DC offset present in the Detector with no signal applied at its RF input. This substantially increases the dynamic range of this VNA in transmission mode to make it comparable to that obtained with Response and Isolation calibration on tuned receiver VNAs (with non-zero IFs).

An analysis of an OSL calibration model that includes Detector offset shows that an additional calibration step is not required to account for Detector offset in reflection measurements.

Response calibration is not as accurate as full 12 error term two-port correction mainly because it does not account for source and load match in the VNA. But it is much simpler and quicker to perform. Its accuracy is acceptably good for most purposes since the source and load return loss in this VNA is better than 25 dB over the HF range (1.8-30 MHz). As noted earlier, external pads can be used where needed to improve transmission measurement accuracy. Judicious use of external amplifiers, on one or both sides of the DUT, can be used to offset the loss of dynamic range normally associated with pads. Selective use of external amplifiers with known gains, with or without pads, can even be used to augment dynamic range.

As noted above, there are no hardware adjustments in this VNA. Either the OSL or the Modified Response calibrations, depending on the measurement mode, is sufficient with the linear Detector in this VNA to provide all needed magnitude and phase information. Frequency calibration is established via adjustment of a software parameter after measuring the DDS output frequency against some known standard such as WWV.

Another feature to be noted in Figure 16, when combined with OSL or Response calibration, is that the test ports (reference plane locations) can be somewhat arbitrarily extended to provide powerful in situ or remote DUT measurement capability, such as shown in the antenna matching example.

For precise measurements of two-port or multi-port networks, any DUT port not connected to the VNA must be terminated in some standard impedance such as 50 Ω. This is necessary to be consistent with the definitions of S-parameters and their subsequent conversion to Y, Z, or H parameters.

Powering

Proper regulation of DC voltages used by the VNA is essential to its performance. The printed circuit board contains the low current, voltage regulators used to supply +5V and –5V to all PCB circuitry except for the signal sources.

The regulator for the +5V to the DDS signal sources and related circuitry is not present on the printed circuit board (PCB) due to the relatively high current requirements. Instead, the regulator is located on a separate external board where thermal management techniques can be best used and thereby minimizing its heating effects and possible coupled noise effects (in the case of a switching regulator) on the sensitive VNA circuitry. The PCB only contains a high frequency filter for the +5V to the DDS signal sources.

Summary

This document explained how a VNA can function internally.  For information on what you can do with a VNA, see HF Vector Network Analyzer - Some Measurement Examples

The performance of the VNA is described in another document.

Notes

For the Couplers and Bridges section, descriptions of the two transformer directional coupler, as used in the Stockton bridge and Tandem Match coupler, can be found in

• Wes Hayward, W7ZOI, “Introduction to Radio Frequency Design,” 1st ARRL Edition, p 156-158.
• John Grebenkemper, KA3BLO, "The Tandem Match - An Accurate Directional Wattmeter," QST, Jan 1987, pp 18-26.
• Paul Kiciak, N2PK, “An HF In-Line Return Loss and Power Meter,” The QRP Quarterly, October 2002, p 17-25.
• The Tandem Match also appears in various editions of The ARRL Handbook and The ARRL Antenna Handbook