This blog covers the next set of Zynq HW videos, some of which I have already blogged about at Path II Programmable Blog 2 - An Introduction to Zynq UltraScale+ MPSoC Hardware
On the whole, this training material is the same as Path to Programmable v1, except with a couple of changes where the Zynq MPSoc differs from Zynq-7000
HW Chapter 5 video: Merging the PS and the PL
- Interfacing the PL to the PS using different AXI interfaces
- An Introduction to AXI
- Cache coherency features
- PS Interconnect
HW Lab 5 - Adding a PL Peripheral
- Add the PL BRAM IP to the block design
- Enabling the PL clock, PL reset & AXI Master interfaces on the PS
HW Chapter 6 video: Zynq DMA Controllers
- How the PS DMA controllers can speed up PS-PL data transfers
- DMA controllers for the PL: AXI DMA IP blocks
HW Lab 6 - Improving Data flow between PL and PS utilizing PS DMA
- Running a DMA test application
HW Chapter 7 video: Creating Custom IP
- Using the Vivado IP integrator & packager
- Creating new IP
HW Lab 7 - Adding Custom IP to Vivado IP Catalog
- Create a new IP project
- Integrating custom HDL files with the auto-generated AXI interface HDL files
- Packaging IP
- Adding the custom IP to the block design
HW Chapter 8 video: Vivado's Hardware Manager
- Vivado Logic Debug IP: ILA, VIO, JTAG to AXI
HW Lab 8 - Hardware Debugging Zynq Designs
- Imported the software project that controls the PWM IP
- Using Vivado's Hardware ILA (Triggers etc.)
- Generating AXI transactions using the JTAG to AXI interface & Vivado Tcl commands
