3GPP stands for Third Generation Partnership Project. This blog deals with the implementation of 3GPP MIMO Decoder on Minized board.
The LTE MIMO Decoder or the 3GPP MIMO decoder implements the uplink MIMO decoding functions for applications following the “3rd Generation Partnership Projects (3GPP); Evolved Universal Radio Access (EUTRA); Physical Channels and Modulation (Release 9), 3GPP TS 36.211 V9.0.0 (2009-12) specification.
Features:
• MMSE MIMO Decoder for spatial multiplexing MIMO systems
• Parameterizable drop-in module for Zynq devices
• Compliance with 3GPP-LTE specification, AXI4-Stream interface
• Key component of Xilinx LTE Baseband Targeted Design Platform
• High resource efficiency
• Supports four receive and four transmit antennas (4x4 spatial multiplexing MIMO system)
• Supports up to four antennas at the base station
• Supports up to four mobiles with one transmit antenna each, in MU-MIMO mode
• Supports one mobile with four transmit antennas in SU-MIMO mode
• Support for receive diversity only mode
• Synchronous clear input • Clock enable input
Block Diagram of a 3GPP-LTE Uplink Receiver:
Implementation steps in Vivado (suitable for MiniZed board):
Creation of new project:
Select XC7Z007SCFG225-1 as the device since it is available on MiniZed board
Click on Create Block Level Design. Click on Add IP and select "3GPP LTE MIMO DECODER"
Right click on the MIMO Decoder block and click on "Run Connection Automation"
Select the Clocking wizard and click OK
Right click and click customize block: Select transmit antennas as 4 and RAM implementaiton option 2
Add VIO and ILA cores as required
Customize the VIO cores:
Add ILA cores to add the outputs of MIMO Decoder IP to be probed
customize the ILA core:
Connect the different CLK signal and the probes signals as shown:
Click on run implementation:
Generate bitstream
Then connect the MiniZed board to the PC with connection to USB JTAG UART port
