Hey everyone.,
ZynqHW_2017_4_lab_4_v11
So let's continue onward with setting up our basics for TCL.
After a brief read through the lab, I plan to use Vivado in tcl mode (non GUI mode). Let's see if we can change ports in a block diagram without seeing a block diagram [hehehe]. Below is a gallery of the output I got from the tcl console. Feel free to have a look at the solution code given at :my repo:
| {gallery} Lab 4 slideshow |
|---|
Where is the BD file located : block diagram |
Opening project : Lab 4 |
Opening block diagram: Lab 4 |
IO ports list: Lab 4 |
A new Reset port attached: Lab 4 |
Validating block diagram and writing the tcl; file for it: Lab 4 |
Sourcing the new Project tcl file: Lab 4 |
Deleting the temp project created...sob: Lab 4 |
So that covers lab 4. It was a small sweet lab !
And onto the next lab, Lab 5!
ZynqHW_2017_4_lab_5_v12
The lab talks about using Block RAMs (BRAMs). They are memory units which can be used for varying purposes, from FIFOs to shift registers. One of the major uses is in the PL, where they are used as memory units for softcore microprocessors (like the MicroBlaze). The Block Memory Generator is an IP used to "optimize BRAM primitives". For example, if we selected Simple Dual-Port RAM, we can save upto 50% of the BRAM resources. It does this through arranging the memory resources according to one of the three optimization algorithms present in it. The next issue we have to tackle, is connecting the BRAM to Zynq PS through an AXI interconnect.
The lab then continues about introducing a PL Clock to the design and a bit about the AXI interconnect. The final block diagram is given below :
So that's it folks, loved how short and concise this lab was. This was the quality I was talking about in the earlier blog. Though would have loved to have a few sections removed from the manual.
Looking forward for the next lab! Until next time!!!
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