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Blog FPGA - 05 - Hardware debuggin and the intro to TCL II
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  • Author Author: nixiefairy
  • Date Created: 3 Feb 2019 11:40 AM Date Created
  • Views 116 views
  • Likes 2 likes
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FPGA - 05 - Hardware debuggin and the intro to TCL II

nixiefairy
nixiefairy
3 Feb 2019

Hey everyone,

And just like that we have reached the end of the lab manual series.

 

Zynq_2017_4_lab_8_v12.pdf

 

The lab starts off from where we had left off earlier. Just to recap -

  • We now have a bitstream containing our PWM IP
  • We also have attached an ILA to monitor transactions.

So now we move onto building our .elf file - on SDK. We have to start by importing one of the codes given in the zip files - LED_Dimmer_Init.c . It's a very straight forward code - and after reading the dma_test.c, this one seems to be like a cakewalk. But for the sake of those reading the code for the first time, I would briefly cover the code -

  • Initialize a ScuGIC interrupt for the PWM IP. Even though it never will be used, it is good practice to do so.
  • Set the brightness level according to the user's preference.
  • Run the LED using a PWM signal - where the level depicts the width of each duty cycle.

Output of the code is :

 

 

Tomfoolery

Just to answer some curious lads out there.

I removed the lines calling the interrupt system setup function  (see here My repo ). Question is - will it still work or not?

Sure enough worked like a charm !

The second part of the lab talks about using the AXI-JTAG Master IP.

The AXI-JTAG Master core is an interactive IP where the user can constantly interact with the bd IPs through TCL.. To be honest, it is a really cool sounding IP. Can be very helpful in debugging especially the AXI IPs. Below are few of the screenshots I've tested out :

 

So that wraps up lab 8. Has given full justice to the AXI-JTAG IP core and the ILA IP core.

 

Zynq_2017_4_lab_9_v2.pdf

 

Nothing much covered in this lab. I really didn't see any important topics being covered. Just like a brief summary of everything we have done in the past 8 labs is being tested here. The size of the course material would be much less intimidating if they removed the number of labs - one being this one.

 

So that finally finished the labs. It has been a very brief journey, but yes, learnt a lot no doubt. Just to briefly cover up the pros and cons of the material :

PROS :

  • Lot of screenshots.
  • Material wise - pretty decent

CONS:

  • Unnecessary headers - a brief run through the labs is required to remove the extra bits. eg. Revision History

A really good training material set to start with. Would definitely suggest this to material for someone who want an in-depth tutorial on today's Vivado. However, for someone who is already experienced with this material or just wants a brief revision I would not recommend this course (way too long and too many screenshots. One gets tired after scrolling through a pdf so much ! )

 

Aah now the fun part - the project.

I am keeping it a secret . It is something one has not tried out before, so it might take me time to release a stable version of it. Regardless of the result, a blog is scheduled to be released on the 29th of Feburary talking about my progress.

So well, mark your calendars I'd say ! Until next time !

Anonymous
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