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Lab 8 - Hardware Debugging Zynq Designs

mconners

We left off last time after creating new IP and adding some debug ports. We added a PWM module, a logic analyzer, and a JTAG port.

 

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This week we got to exercise those pieces.

 

First thing we did was export the hardware to the SDK workspace and created an empty application.

 

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So we created the LED_Dimmer_Int program. We just added existing source from the provided source files directory. You might be able to make out the PWMIsr method there. This is a console application that we ran through miniterm, any number input between 0-9 would change the brightness of a built in LED. Any non numeric character would call the PWMIsr method. We could interact with the board through a console.

 

 

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So that was really the first test.

 

Secondly, we were able to monitor the signals on the board using a built in logic analyzer:

 

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We were also able to set a trigger that would detect the interrupt:

 

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That was pretty interesting and I can see where there would be a great deal of usage for this during development.

 

One of the things that was emphasized in this module was the iterative nature of the development. I appreciated this, because as a software developer, I develop my code in much the same manner.

 

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This reminds me of the RED-GREEN-REFACTOR methodology of TDD (Test Driven Development) that I employ. Where you

1) Write a failing test - RED

2) Write just enough code to make it pass - GREEN

3) Refactor the code to clean it up and ensure all the test still pass

 

 

After playing around with the logic analyzer for a while they showed how to use TCL (remember that) to exercise the board through the JTAG port.

 

So in this module, we found 3 different ways to interact with the IP

1) Programmatically, through the SDK and PS (Processing System), which we had been doing all along

2) Through the logic analyzer

3) Through the JTAG interface.

 

At the end of the module they had us remove the JTAG interface through the GUI.

 

This was a very informative module, the final installment of the first set of will be more TCL, I'm assuming we will probably remove the Logic Analyzer using TCL.

 

Randall sent an email today saying he'd be sending the next batch of training materials soon, so I'm glad I paced myself and will be ready for the next batch.

 

Until then ...

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