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  • Author Author: mconners
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Labs 5 & 6

mconners

Finally starting to access the PL

 

I grouped labs 5 & 6 together because they really are 2 parts of a single lab. Lab 5 was adding a Block Ram to the Processing System using the AXI Interconnect System, Lab 6 was actually Programming the FPGA to create the IP, and the second half was compiling a program and installing it on the CPU to execute some DMA tests, record the timings, and calculate the speed savings using Interrupt DMA. One of the enlightening things about this lab was seeing all of the different types of IP designs they provide for you. I'm not sure of the exact number, but they have FFT and DFT blocks, FIFO's, Ethernet Blocks, Video Frame Buffers, Processor Cores, and much, much more.

 

 

 

image

 

If you look at some of my earlier blogs, you may remember that the above diagram only contained the ZYNQ7 Processing System. In the lab we added the Reset Block, the AXI Interconnect, the BRAM Controller, and the Block Memory Generator. It's a lot of steps so I won't go through them here, but it's not a difficult process to add each of the components. I did not have to draw the interconnect lines, it did that when I added each of the blocks. So that was nice. It also took care of arranging the blocks for me.

 

image

 

 

The above is a screenshot of the SDK. They had a pre written program to exercise the Block Memory they had us add. We did make use of a new button this time. Right below the help link, there is a button with a red arrow and 3 green boxes. We clicked on that to program the FPGA. After that we hooked up the console below. Flashed the processor, and exercised the newly added IP.

 

 

image

 

In the above example, I had chosen an 8192 block size for a DMA transfer of BRAM to BRAM, which resulted in 24x improvement over having the CPU copy the data.

 

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The above screen capture is more of the same. I pretty much tried all the combinations.

 

That's it for Labs 5 & 6. Really just a baby step that we will build on. Lab 7 is about creating Custom IP so that should be a bit more interesting.

 

I am enjoying this, and I'm glad I'm remembering what we did in previous labs, so their technique  is working. The material and exercises are not particularly difficult, but the ZYNC7 processor is a very complex device. There are a lot of possible configurations and uses so we'll see where this goes.

 

That's all for now. If you have questions, feel free to ask.

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  • Nice update Mike.

     

    I am curious, how much time did you spend reading the material and then how much time did it take you to implement each lab?

     

    DAB

  • in reply to DAB

    Hey DAB,

     

    Each lab is preceded by a video, along with a set of slides. I've been to a number of 1-2 day seminars put on by manufacturers like ST, and this seems very comparable. One of the testers commented that it seems like a semesters worth of material, but to be honest, what we have been provided so far seems like it would be a 2 day seminar by Avnet or Xilinx. Not that that is bad in anyway. Lab 5 seemed like it would be the last lab of Day 1 and lab 6 seems like it would be the follow on the next day. I looked at what wrote up and I have to say he went above an beyond the info that is supplied in the training and did a fantastic job. I've debated internally about whether to go into that depth, or to simply blog about each lesson as it's presented and then supply a detailed write up of what I've learned at the end. So, to ultimately answer your question, I'd say about 30 minutes of lecture, followed by 30 minutes of lab, followed by about 30-45 minute of review and documentation on my part at the end.

     

     

    Mike

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  • in reply to DAB

    Hey DAB,

     

    Each lab is preceded by a video, along with a set of slides. I've been to a number of 1-2 day seminars put on by manufacturers like ST, and this seems very comparable. One of the testers commented that it seems like a semesters worth of material, but to be honest, what we have been provided so far seems like it would be a 2 day seminar by Avnet or Xilinx. Not that that is bad in anyway. Lab 5 seemed like it would be the last lab of Day 1 and lab 6 seems like it would be the follow on the next day. I looked at what wrote up and I have to say he went above an beyond the info that is supplied in the training and did a fantastic job. I've debated internally about whether to go into that depth, or to simply blog about each lesson as it's presented and then supply a detailed write up of what I've learned at the end. So, to ultimately answer your question, I'd say about 30 minutes of lecture, followed by 30 minutes of lab, followed by about 30-45 minute of review and documentation on my part at the end.

     

     

    Mike

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  • in reply to mconners

    Hi Mike,

     

    I totally agree with you, the pace is easy to move at! It's great to see what you've worked on in these labs, I still have to do them. Very cool that the labs will take us into using these other bits of IP. I was not sure what to blog either, so figured that since I'm a novice I might take it slower. I reckon it's really helpful for readers that there are different speeds of information and different levels of experience.. I always like to read several textbooks if I'm learning something new.. and I suspect that anyone who reads these blogs might do the same. It's just like having many books : ) I'll be interested to compare your output screenshots above with what I get when I reach this point.. curious to see the same cycle counts : )