P2P – Module 1 – Lesson 1 Notes

Introduction

This is an introductory video that is about 9 minutes in length.  The training is branded as AVNET “Speedway”, and is taught by Josh Foster.  The module 1 objectives are:

• Understand how to use Vivado's tools with the Zynq-7000.
• Learn about the integrated ARM Cortex A9 processor core.
• Use the Xilinx embedded tools to design and build a system - including both the integration of pre-built IP modules and also developing our own modules.  And then some training on how to run and debug everything.

The course objectives are pretty comprehensive, as the course includes both hardware and software development.

Agenda

There are a total of 9 labs. And they’re using Tcl, which is an OLD scripting language developed in the 1980s by John Ousterhout.  A little history here: https://www.tcl.tk/about/history.html.  I last used Tcl on an embedded project using Wind River’s Workbench in the early 2000s.

Why Develop a FPGA Design?

There are a lot of good reasons to off-load stuff from a CPU into a FPGA.  Some of the reasons include:

• High CPU utilization.  They mention 90% as a threshold, but in my experience I would be terrified if a design was loading the CPU at that level.  At that level of utilization, interrupt timings are likely not being met.  My personal experience is to not exceed 60-70%.  But maybe that is just me.
• If your software is doing CPU intensive, recurring tasks.
• Interrupt handling is delayed.  Real easy to screw up communications protocol when that happens.

Software is Inherently Sequential in the Embedded World

The lecture makes the case that software engineers always doing things with sequential logic – which is not really true.  For example, we use .NET and C# at work and there is a lot of support for asynchronous (parallel) threads.  Also, statistical languages such as R and Python support parallelism.  Of course, this code usually runs on powerful multi-core Intel or Amd processors, which generally aren’t found in embedded applications.  But in a sense, any time you have a task scheduler that supports multiple priority levels in your embedded OS, or if you can offload some work to a lot of the "peripheral manager" units found on many embedded CPUs, you do get some amount of parallelism.

A Hardware Solution Can Better Support Parallelism

Typically, using hardware such as a FPGA will enable parallel processing.  And it’s also true that implementing parallel processing in hardware will be generally more more efficient than in software.  But in hardware, a memory management system is required to resolve concurrent memory read/write.

Marketing Slide For the Zynq Product Line

This is pretty neat, didn’t realize that what we’re going to use was the first all programmable SOC family. That is a lot of design wins.  And a lot of ecosystem partners.  The product was introduced in March 2011, so it's been around for a while.

System Overview

There's a lot of horsepower on-board:

• Programmable logic
• Built in processors - up to 1GHz clock speed.
• "Massive" DSP capability: up to 1000 GMACs!
• High throughput to direct connections
• High performance I/O.
• Gigabit transceivers (up to 12.5Gbps)

The board design makes it possible to move previously software-only (“C” blocks) into hardware (“HDL” blocks)..  There is mention of co-processor implementation but don't understand where or what product models incorporate co-processors.

The hardware logic can be updated in realtime.  Intensive algorithms (such as  SDR – software defined radio, encryption, and data processing) can be implemented in hardware - and then controlled and coordinated by the software.

A software designed radio  what I want to do for my project. Don’t know (yet) if there is sufficient A/D and D/A resolution and sample/conversion speed to support 2m (about 145MHz) and 70cm (about 440MHz) for both direct down and up conversion – creating a transceiver.  Will be fun to find out.

The board supports reduced power modes:

• Lower static and I/O power needs.
• Ability to adjust clock and timing frequencies.
• The ARM processor has built in low-power states.

The claim is a 50% reduction in power consumption compared to traditional multi-chip solutions.  I've had the misfortune to have been in the "need too much power" battleground before, in one case with a battery powered processor that burned way too much energy – and we had to implement a complex “sleep mode” using both hardware and software.  Not fun.

Reduced EMI is another benefit. EMI is always an issue with embedded medical designs.

The tools support software and hardware co-development.

Eco-System and Security

Wish high security wasn’t necessary but these days … it’s nice to see it.  Zync boots from a single secure hardware source.  They made a reference to a separate detailed security presentation – maybe that will be later in the course.  Having two or more boot methods makes it possible for a hacker to create a hidden back door into your system.

They have Hypervisor and trusted zone solutions as well.  And there are a lot of supported solutions from partners:

Middleware:

• Timesys (a real-time Linux implementation)
• MathWorks (MathCAD)
• Wind River
• Enea

Operating Systems:

• Nucleus from Accelerated Technologies - now Mentor.
• QNX
• ENEA
• VxWorks

Hypervisors:

• Open kernel labs
• Green Hills
• Wind River
• Open virtualization

Marketing Slide - Device Portfolio

This is a really nice slide that shows the relative capabilities of the product line.  All parts in the family share the same A9 core.  Ahh, looks like A/D only 12 bit.  Don’t see D/A.  Maybe there is something available in the DSP or on the A9.  Guess I'll learn that at some point.  My backup SDR plan was to support the recently opened very low (600m and 2200m) bands.  Much lower processing needs at hundreds of Kilohertz compared to hundreds of Megahertz.…

Not too surprising that a product that has a “mini” prefix is the entry level product.

Lots of prototype and products!  Including:

• ZedBoard
• MicroZed
• PicoZed
• UltraZed
• Zynq MMP
• Zynq Mini-ITX

And this lecture indicates at the end that we should complete a “developing zync software” online speedway.  Will have to dig up the link for that.  Will post what I find.

Lecture Summary

This was a very informative lecture that gave me a basic understanding of the Zync software/hardware world, and also about the many partners that provide support middleware and real-time operating systems.