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Path to Programmable
Blog Path to Programmable - Blog 4 - TCL, AXI, DMA, BRAM
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  • Author Author: rsc
  • Date Created: 28 Oct 2018 5:13 AM Date Created
  • Views 944 views
  • Likes 7 likes
  • Comments 2 comments
  • path to programmable
  • minized
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Path to Programmable - Blog 4 - TCL, AXI, DMA, BRAM

rsc
rsc
28 Oct 2018

The MiniZed training is getting more complicated.  Several new items have been discussed including TCL, AXI, DMA, and BRAM. 

Lab 3 objectives:

image

This lab is designed to set up the hardware configuration in Vivado and the SDK for the actual components and features found on the MiniZed board.

This is similar to the include file for a microprocessor GPIO mapping you would use with a typical compiler, although much more complicated.

There is a nice "wizard" type interface with tabbed pages to let you visually see how the peripherals are mapped and connected to each other.

Vivado has a very visual interface that makes it easier to comprehend how the individual components are interacting.

image

Lab 4 objectives:

image

This lab showed how to manipulate the Vivado program by using a scripting feature called TCL.  Several of the tasks from the first few labs were "automated" using TCL commands similar to a batch file, and saved in a .tcl file.

I might be dating myself, but the TCL interface is much like the COM (Component Object Model) interface I used to have windows programs "talk" to each other.

Lab 5 objectives:

image

This part of the training is new to me.  I've never had to worry about mapping memory since the days of EPROMs .  There are multiple ways to connect peripherals depending on the speed and features required for your configuration.

The AXI interconnects are used to interface the peripherals in a master/slave relationship.  There are high speed and low speed AXI ports, and you can configure the data size and memory parameters for each port.

I watched this video 3 times and did the lab twice to figure out what was going on.

image

Lab 6 Objectives:

image

Lab 6 is a continuation of lab 5 by using the different memory banks DDR3 vs BRAM to execute code and showing the speed differences.  I'm still digesting this one.

image

This training is making my brain hurt.  At least the Avnet training is progressing in a way that shows how the puzzle pieces of the MiniZed fit together. 

Some manufacturers throw a dev board at you with just one example program that utilizes all the board features at once and it's up to the user to figure out each section.

Happy coding.....

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Top Comments

  • snidhi
    snidhi over 7 years ago +1
    hahaa funny to say... makes your brain hurt.......... It can be a bit overwhelming and one can easily goto into DATA Overload 'Brain death situation'
  • Fred27
    Fred27 over 7 years ago +1
    I'm glad it's not just me that's finding some of this hard to take in. The lab examples are easy to follow but don't teach you that much. The videos (especially the AXI one) are hard going.
  • Fred27
    Fred27 over 7 years ago

    I'm glad it's not just me that's finding some of this hard to take in. The lab examples are easy to follow but don't teach you that much. The videos (especially the AXI one) are hard going.

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  • snidhi
    snidhi over 7 years ago

    hahaa funny to say... makes your brain hurt..........

    It can be a bit overwhelming and one can easily goto into DATA Overload 'Brain death situation' image

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