The objectives of Lab 7:
https://www.xilinx.com/products/intellectual-property.html
The basic objective of the last few labs in this training module is to light up an LED and control it with a PWM output.
In addition, the JTAG interface was explored, along with ILA debugging. A few hours into this session, I could enter a number into a
terminal program, and the LED would change brightness from off to full-on. The ILA is a logic analyzer GUI that utilizes the
dual-port memory to view signals real-time. In this case, it was used to view a trapped interrupt signal. Very cool.
I am amazed at the auto-connection and routing routines in Vivado. I've spent hours making nice looking schematics that only takes seconds here.
Lab 9 started off well.....
Then I ran the Lab9 TCL script...….
12 errors, 551 warnings, 58 critical warnings, 1,137 info, 207 status messages.
[DRC INBB-3] Black Box Instances: Cell 'Z_system_i/axi_mem_intercon/m01_couplers/auto_ds' of type 'Z_system_Z_system_auto_ds_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
[Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
[Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Xilinx/1234-oj1A
The TCL script added a bunch of things, I just need to figure out the error messages.
Clear as mud?
Scott
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