Before Starting to work on Minized with Xilinx SDK , we need to get Acquainted with at least some Hardware Aspects of Minized ,in order to prevent possible Confusion.
If you guys have Already followed my Hardware Design Posts , you can skip to "Now What are we Going To Do with Software Development" section at the Bottom
For those who are new to Minized I recommend you guys to first Go through this Post for getting a big Picture perspective :
First of All What is Minized Board ?
Minized is Xilinx Zynq XC7Z007S based Programmable SoC (System on Chip) , which has a Processor Subsystem (PS) of ARM Cortex A9 core and the Programmable Logic (PL) based on Xilinx( Artix 7 for Minized )fabric.
What is Programmable SoC ?
It is simply a microController like device but which Large Number of Peripherals (UART, Bluetooth,WiFi etc)and High Computing Power CPU core (ARM cortex A9) and in addition to this It has a Programmable Area (Similar to that in FPGAs) which can be used to build or Design any Hardware ( such as USB controller device , Counters,Multiplexers etc)or Other Custom Blocks (Adders , DSP systems etc).
It can be Easily Understood With Help of Architecture in Below.
Note: Below Architecture is of Zynq7000 which has 2 Cortex A9 cores where as Minized based on Zynq7007s has Single ARM Cortex A9 core
Architecture of MiniZed PSoC :
Here It can be seen as a Device with Two Blocks (Areas) tightly Coupled (connected) : 1.Processing System (Gray Area) and 2. Programmable Logic (Yellow Area)
Processing System (called as PS , informally call it CPU or MCU ) works just same as a normal Micro Controller or a Small CPU with Peripherals (similar to BeagleBone Black)
Programmable Logic (called as PL )Works as a FPGA (Informally call it as FPGA)
The Interesting thing is Both Blocks are Independent in Functional but talk to Each other as shown in below fig
The ARM core in PS talks to the Device(Custom Logic or IP core) through AXI Interfaces we Built in Programmable Logic using the Memory Space Addressing (Simply as a Location with Address in DDR memory)
It means , A software Designer can See the Device in PL fabric as a memory location , Interact with it in same way as that of with Memory .
The Blocks or Devices in PL talks to ARM core by sending data to DDR memory through the Registers Designed as sort of Middle man or Interfacing by Mean of AXI .
In this way these both Guys - Our PS and PL ( FPGA ) who are unknown to each other but talks as if they are on same channel but Actually their Different Channels are made to Appear as Same by the DDR Memory and Registers as Middle men for them.
How You Can Use IT ?
Because it has Both PS (CPU ) and PL (FPGA) in it ,
We can Use the PS (CPU) as microController with Peripherals or Small Computer like BeagleBone Black or Raspberry Pi , True ! It (ARM cortex 9)runs on Peta Linux (A flavor of Linux)
We can Use th PL (FPGA ) the Same way what we can Do with a FPGA
Creatively , we can use both for instance for some custom Design on PL(FPGA) we can use the Peripherals on PS (CPU) (Such as WiFi ) and use it as combined application ,
Possibility is endless !
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For Working On Minized , we need :
1.)Xilinx SDK which comes along with Vivado Design Suite.The Below video shows How to Install Xilinx Vivado with SDK in Linux (ubuntu):
2.)Putty or Teraterm , so that you can communicate with the Minized Board through Virtual Serial COM port
That's it.Now You got all the Required Tools , Now you can Explore the Minized Board to its Full Potential using them.
Now What are we Going To Do with Software Development :
After Completing Hardware Development in Vivado as seen in my Previous Posts relating to Hardware Labs , we generate a Bit Stream File.
What is a Bit Stream file
In Programmable Logic World (FPGAs) , hardware is programmable in the Sense that the wires that are routed between different blocks is Configured (Based on the Technology ) and predefined logic blocks are configured to implement the Design (usually specified in HDL).
Bit Steam is the mapping to the device such that the Routing of Wires and Logic Block configuration is achieved.
It is generated by EDA tools(eg. Vivado) by synthesizing the design and checking for any timing constrains given(eg: used in cases where Some signals are to be reached within specified time delay like 0.5ns etc. )
The PL block is structured (programed) into that Hardware Design by loading that Bit Stream into SRAM which connects to the Programmable Interconnects there by implements that Design on Hardware.By Exporting the Hardware into the SDK , Vivado Directs SDK the Peripherals available in the Design with their Addresses to interact with it by means of Hardware Defination File (.hdf file).
So that When we start working with SDK , you just need to work on the Address locations just as you would in any Embedded System or MicroController Programming, This Approach Helps the Software Designer to get rid of Hardware Complexities and Signaling Problems in Low Level , It gives you an Abstraction to see the Whole System with All peripherals as similar with Unique Address Locations and Load or Store Data into that Location Accomplish a Complex Task of Interfacing that Mysterious Hardware Block.
In the Next Posts we can see , how easy it is to use a block already Designed in Hardware Labs in terms of simple C program.
So what you Need now is to have basic Understanding of C programing.
If you like to review your C programing Concepts , I found this Page very Helpful , even though it was Given for Learning C for ARM cortex M , It servers its Purpose Better for Us also.
Embedded Software in C for an ARM Cortex M -- Valvano and Yerraballi
That's it, for this Post,In the Next Post we will jump into Working on Minized 
Happy Learning !