Chapter 8 Video - SDK Project Management
This video was about project management in Xilinx SDK: workspaces & how to share/export them, how to import C/C++ files and set up repositories.
Lab 8 - SDK Project Management
The export tool allows users to export their projects, breakpoints, launch configurations etc. to archive files.
The exported files can then be imported to a new workspace/different computer. The import tool also allows C/C++ files to be imported.
Chapter 9 Video - Interrupts
Zynq Interrupts are classified into 3 main types: software generated interrupts, private peripheral; interrupts and shared peripheral interrupts.
Software-generated interrupts – 16 interrupts per processor. They can interrupt one or both of the Zynq SoC’s ARM Cortex-A9 processor cores.
- Shared peripheral interrupts – A total of 60 interrupts can come from the I/O peripherals, or to and from the programmable logic (PL) side of the device. They are shared between the Zynq SoC’s two CPUs.
- Private peripheral interrupts – 5 interrupts in this category are private to each CPU eg. timer, watchdog & a dedicated PL to CPU interrupt.
Similar to other processors, the interrupt handler services each interrupt by looking up the corresponding entry in the vector table and pushes register contents to the stack.
The video concluded with a couple of general tips for handling ISRs.
Lab 9 - Interrupts
In this lab, we created a new empty application and imported a file that was included in the training material. The instructions were to modify the file to include drivers for the SCUGIC and exception handler. After adding a couple of macros and variables, we added the callback function for the ISR. To setup the interrupt system, initialize the controller driver, setup the handler, enable the interrupt and initialize the exception table.
The image gallery contains a refresher on how the hardware was wired up in Module 1:
| {gallery} Vivado Block Design |
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Interrupt_Out signal from the PWM block |
The PWM block interrupt goes to a Concat block (that combines the different interrupt signals into a bus), which feeds the Zynq. Note that the PWM block is mapped to the LSB of IRQ_F2P |
The LSB is assigned ID '61' |
Configuring the interrupt handler in Xilinx SDK - interrupt ID 61. |
Running it results in this:
Setting a value that isn't 0-9 makes the interrupt line go high (in hardware), which then propagates to the ARM core through the GIC, executing the code in the callback.