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Blog [PP-06] Lab 3 - Configuration of MIO peripherals and generation of test applications
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  • Author Author: kk99
  • Date Created: 29 Oct 2018 8:11 PM Date Created
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[PP-06] Lab 3 - Configuration of MIO peripherals and generation of test applications

kk99
kk99
29 Oct 2018

The Lab 3 is continuation of previous Lab. In this part we will learn how to set up additional peripherals like QSPI, USB and SD. From the SDK point of view we will learn how to use example test applications.

 

First step is customization of Zynq ARM core by enabling QSPI, USB and GPIO in Vivado block design. It could be done from MIO Configuration page from ZYNQ7 PS. At the end we need to re-launch synthesis, implementation and generation of bitstream. After that we could export a hardware to SDK. Below are example screenshots from MIO configuration.

image

In the SDK we need to add two new application projects for memory and peripherals tests. After compilation we could run each application on target board. To add a new application project we need to choose: File -> New -> Application Project. Then we need to enter project name and select to use existing BSP. From templates we need to select to Memory/Peripheral Tests application.

image

Below are outputs from each application.

image

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