In this lab we will learn how to create a custom IP, add it to the IP catalogue and use it in the design.
1. How to create a new AXI peripheral
Please select from main bar option: Tools->Create and Package IP New IP. There will appear a wizard.
Please select option to create a AXI4 peripheral.
Enter package name, display name and description.
Default interface settings are fine for this module.
Press Finish. New IP will be added to IP catalog.
2. Modify the new IP Project
At this step we import user logic HDL: PWM_Controller_Int, connect to slv_reg0 from the AXI interface and PWM outputs to top-level.
Please select Window -> IP Catalog then search for "PWM" and select Edit in IP Packager.
Now we need to import file PWM_Controller_Int.v from Speedway support documents. Please click Add Sources from Flow Navigator menu. Please select Add or create design source then Add Files. Make sure that option Copy sources into IP directory was selected.
Now we need open file PWM_w_Int_v1_0.vhd and declare PWM_Controller_Int in component declaration section of PWM_w_Int_v1_0.vhd. Additionally we need to add also user logic section. Then we need to connect inputs and outputs according to below screens:
Now we could run synthesis.
3. Package IP to the IP catalog
Press Package IP from Flow Navigator menu. Please change Life Cycle to Production in Compatibility menu. Add Files Group we need to two standard groups for Simulation and Synthesis with source HDL files. At Customization Parameters tab we need to change visibility of PWM_PERIOD parameter. Add tab with Ports and Interfaces we need to define interrupt by choosing: Interrupt_Out->Auto Infer Single Bit Interface. After that we could click Review and Package tab and choose option Re-Package IP.
4. Add IP to project
Now we could add this IP block in our design then please choose option run connection automation. After that we need to enable Fabric interrupts in ZYNQ7 PS then connect Interrupt_Out from the PWM_w_Int_v1.0 IP block to the IRQ_F2P[0:0] on the ZYNQ7 PS.
Last thing is to connect PWM outputs. We will use here a Integrated Logic Analyzer IP from IP catalog. We need to configure it to have 4 probes with correct widths and connect them to the PWM outputs. Connect LED to probe0, PWM_Counter to probe1, DutyCycle to probe2 and Interrupt_out to probe3. Connect the clk to FCLK_CLK0.
In the next lab we will exercise a debug interface and add a software application to interact with this custom IP.