Path-to-Programmable Trainees: How's It Going and Next Steps

Hi Randall,

I've been surprised how well the training is written and presented.

I've done a fair bit of training material preparation in the past, and it's always a fine balance between satisfying the teaching requirements, reducing the risk of errors and frustration, and recognising that engineers will always go off on their own and ignore the steps occasionally : ) it's just a natural part of being an engineer, to want to explore and learn more, so the trainer anticipates that.

In terms of the technical content, so far there is more on working with the Zynq rather than actual VHDL, but I had a feeling that would be the case since it's not feasible to learn much VHDL at the same time as the massive task of learning how the SoC works and how to use it in Vivado. I think for the Zynq/Minized, we're learning what is needed in an acceptable order so far.

I wouldn't say the course is easy, there are some concepts that have to be just accepted until the user gets further and is in a position to go back to understanding those concepts, but it is manageable with very little prior knowledge needed.

The blogs are taking a while to write, because there is a balance between learning and then reporting what we've been doing, and sharing some aspects of how to do it. It has been very helpful that we're all working on this at the same time with a common goal paced out each week.

I think it will be sufficient for a project.. I've started thinking about what I'd like to do for that, I still need to decide.

In terns of the hardware, the Minized is nice.. I'd like to integrate it into a few projects.

Hi Randall,

I've been surprised how well the training is written and presented.

I've done a fair bit of training material preparation in the past, and it's always a fine balance between satisfying the teaching requirements, reducing the risk of errors and frustration, and recognising that engineers will always go off on their own and ignore the steps occasionally : ) it's just a natural part of being an engineer, to want to explore and learn more, so the trainer anticipates that.

In terms of the technical content, so far there is more on working with the Zynq rather than actual VHDL, but I had a feeling that would be the case since it's not feasible to learn much VHDL at the same time as the massive task of learning how the SoC works and how to use it in Vivado. I think for the Zynq/Minized, we're learning what is needed in an acceptable order so far.

I wouldn't say the course is easy, there are some concepts that have to be just accepted until the user gets further and is in a position to go back to understanding those concepts, but it is manageable with very little prior knowledge needed.

The blogs are taking a while to write, because there is a balance between learning and then reporting what we've been doing, and sharing some aspects of how to do it. It has been very helpful that we're all working on this at the same time with a common goal paced out each week.

I think it will be sufficient for a project.. I've started thinking about what I'd like to do for that, I still need to decide.

In terns of the hardware, the Minized is nice.. I'd like to integrate it into a few projects.