Learning Single Board Computers

Then I think about how I would do it nowadays.    I'd probably select a processor for which there is a fairly large code-base.  Z-80, 68000, 8051, unless this is some kinda art project.  Then I would get a computer-that-worked.  One I/O line of the c-t-ws is attached to the reset line of the computer-under-development.  Master-slave in the pre-pc language of the day.  Inbetween the boxes is a dual-port SRAM.  These were (o.c.) static and were what the watch-battery was for.  At different times, each box accesses the SRAM.  The physical connection to the slave is using the DIP form-factor of the chip.  We use a dip ribbon cable for the attach.  When we have figured out what we want in terms of code at these locations, we ditch the dual-port ram if favor of a ROM which will be an EEPROM.  We need to turn the address and data lines of the SRAM into two that are time-multiplexed.  We need to jock the control terminals so that only one set of buffers is active at a given moment.

We can attach 244 types to the address lines and select or enable only one buffer (or buffer stack) at a time.  We can attach 245 types to the data lines and select or enable only one bidirectional buffer at a time.  The signal that actuates the selection logic comes from the master.  The more the merrier.  We can ping-pong for a back-channel.  We can establish separate control and data channels.

These processors go to an initial address for code when they come out from reset.  That's where you want to put the memory on the slave card.  The other port attaches to the computer-that-works.  If the c-t-ws has lotsa I/O lines to accommodate the parallel busses of the SRAM, it can be attached the same way.  If I/O pin count is sparing on the c-t-ws, we can use a counter chip on the address lines of this port to degenerate it into a stack, which is a no-worry, as we were planning upon using it just as a sequential pipe anyway.

Rainy-day-play has us holding the slave under RESET with the master, loading the SRAM with code from the master, detaching the master, then releasing the slave.

Then I think about how I would do it nowadays.    I'd probably select a processor for which there is a fairly large code-base.  Z-80, 68000, 8051, unless this is some kinda art project.  Then I would get a computer-that-worked.  One I/O line of the c-t-ws is attached to the reset line of the computer-under-development.  Master-slave in the pre-pc language of the day.  Inbetween the boxes is a dual-port SRAM.  These were (o.c.) static and were what the watch-battery was for.  At different times, each box accesses the SRAM.  The physical connection to the slave is using the DIP form-factor of the chip.  We use a dip ribbon cable for the attach.  When we have figured out what we want in terms of code at these locations, we ditch the dual-port ram if favor of a ROM which will be an EEPROM.  We need to turn the address and data lines of the SRAM into two that are time-multiplexed.  We need to jock the control terminals so that only one set of buffers is active at a given moment.

We can attach 244 types to the address lines and select or enable only one buffer (or buffer stack) at a time.  We can attach 245 types to the data lines and select or enable only one bidirectional buffer at a time.  The signal that actuates the selection logic comes from the master.  The more the merrier.  We can ping-pong for a back-channel.  We can establish separate control and data channels.

These processors go to an initial address for code when they come out from reset.  That's where you want to put the memory on the slave card.  The other port attaches to the computer-that-works.  If the c-t-ws has lotsa I/O lines to accommodate the parallel busses of the SRAM, it can be attached the same way.  If I/O pin count is sparing on the c-t-ws, we can use a counter chip on the address lines of this port to degenerate it into a stack, which is a no-worry, as we were planning upon using it just as a sequential pipe anyway.

Rainy-day-play has us holding the slave under RESET with the master, loading the SRAM with code from the master, detaching the master, then releasing the slave.