Learning Single Board Computers

You still need an eraser but that one I linked to was only £6 or $10

Were those tubes of parts cheap I didn't look?

No need to buy tons if you are doing a specific project.

The instructions state what chips you need and  basically you need a socket and a small decoupling capacitor for each (0.1uF ceramic cap)

Some fine wire to wire it up and what ever else they mentioned in the circuit diagram

For a single prototype you may be better wiring it up using square pad board. Look at the stuff Ben Heck was using in that video I linked to!

should be no more than say £5 for  suitable size

Do I need the 28C256 when I make this eprom programmer?(MEEPROMMER (EN) | Ich bin zuständig!) Or is that just what eprom he is programming?

Thanks,

Nehemiah

Also what gauge wire do you recommend for this?

Thanks again,

Nehemiah

If you are using wire wrap for connections, use 30 gage Kynar wire.

If you are soldering, anything from 22 gage to 26 gage should be good.

For prototyping I like stripboard.

The 28C256 is an EEPROM - this is electrically erasable so it does not need a UV erasing light.

I don't think you don't need it to operate the programmer, it is just an example of what can be programmed.

You should be able to use an equivalent EEPROM to your EPROM to eliminate the need for an eraser.

I've made homemade 8051 and mc68000* sbcs three decades or so ago.  Big fun!  I used parallel eeproms like what Dennis was describing.  Making a homemade eprom programmer would have been tough.  It needs precise timing, super voltages, some manufacturers weren't telling the programming recipe.  The form-factor similar EEPROMs and SRAMs were more tractable.  I was able to make an eeprom programmer out of a ZIF socket, some latches, a counter and a USART chip.  Assembled electronics was far more expensive then, and we didn't have EBAY.  If you use SRAMS, you can toss in a watch battery and a shottky diode to keep them stable when the main power goes down.  You can degenerate a SRAM into a FIFO or LIFO with a counter on the address lines.  You can dual-port (or, one better, dual-port ping-pong w two ram chips) an SRAM with buffer chips and a wee bit of logic.  Then you could asymmetrically (or symmetrically) multiprocess.

Also , you can stack two chips on top of each other and solder each identical pin together save an address line.  These come out on a couple soldered-on w/w wires.  Double the capacity, only use Z space!

Stick with CMOS processors, they tend to allow static operation.  DRAM uPs have a low speed in the range of MHz/10 - MHz.

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Earlier, I presumed, reasonlessly, perhaps, that we were limiting the discussion to 8-bit uPs.

You could try wire-wrapping.  On EBAY you can get a gun and a stripper and wire and sockets and headers and perfboards and j-pins for low prices.  The prices of this stuff aren't in free-fall, unlike modern stuff.  The supply connections, including the local decouplers need to be made with something heavier.  Solder braid can be used for this.  Try to get a board with a ground-plane.

Also, ya need ta get either stand-offs or card guides.

Then I think about how I would do it nowadays.    I'd probably select a processor for which there is a fairly large code-base.  Z-80, 68000, 8051, unless this is some kinda art project.  Then I would get a computer-that-worked.  One I/O line of the c-t-ws is attached to the reset line of the computer-under-development.  Master-slave in the pre-pc language of the day.  Inbetween the boxes is a dual-port SRAM.  These were (o.c.) static and were what the watch-battery was for.  At different times, each box accesses the SRAM.  The physical connection to the slave is using the DIP form-factor of the chip.  We use a dip ribbon cable for the attach.  When we have figured out what we want in terms of code at these locations, we ditch the dual-port ram if favor of a ROM which will be an EEPROM.  We need to turn the address and data lines of the SRAM into two that are time-multiplexed.  We need to jock the control terminals so that only one set of buffers is active at a given moment.

We can attach 244 types to the address lines and select or enable only one buffer (or buffer stack) at a time.  We can attach 245 types to the data lines and select or enable only one bidirectional buffer at a time.  The signal that actuates the selection logic comes from the master.  The more the merrier.  We can ping-pong for a back-channel.  We can establish separate control and data channels.

These processors go to an initial address for code when they come out from reset.  That's where you want to put the memory on the slave card.  The other port attaches to the computer-that-works.  If the c-t-ws has lotsa I/O lines to accommodate the parallel busses of the SRAM, it can be attached the same way.  If I/O pin count is sparing on the c-t-ws, we can use a counter chip on the address lines of this port to degenerate it into a stack, which is a no-worry, as we were planning upon using it just as a sequential pipe anyway.

Rainy-day-play has us holding the slave under RESET with the master, loading the SRAM with code from the master, detaching the master, then releasing the slave.