Blog #2 : Understanding Architecture of Cortex M4F and SAM E51

In this blog, I am going to explain architectures of  Cortex M4F and  SAM E51  in detail.

1. RISC ARM Cortex M4F Architecture

The kit contains microcontroller ATSAME51J20A which is based on 32-bit RISC ARM Cortex-M floating point unit.

1.1 RISC

This ARM's RISC(reduced instruction set computer) is a modified Harvard architecture machine and might require more instructions than CISC(complex instruction set computer), which is contrary to its name 'reduced'.  The instruction set architecture is a load-store architecture or a register-register architecture, thus, insructions are 

• load and store between memory and registers, wiz., memory acces
• operations which only occur between registers like ALU

1.2 Cortex Processor

 Being based on Cortex M4F, the microcontroller is based on ARMv7E-M architecture. So, basically it would be having 3 stage data pipeline with 12 cycle interrupt latency, banked stack pointer,  handler mode, thread mode, interruptible-continued instructions and 16-bit Thumb instruction set besides 32-bit ARM instruction set, doing ISA operations of 32-bit-wide data in 32-bit-wide registers with 32-bit addresses. The Thumb instruction set can have 2-byte or 4-byte encodings requiring 2-byte or 4-byte alignment respectively. Below is the structure of the Cortex-M4 processor excluding FPU

Source : ARM 

The architecture reserves address space 0xE0000000 to 0xFFFFFFFF for system-level use. It contains four external Advanced High-performance Bus (AHB)-Lite bus interfaces - ICode (instruction fetches from 0x00000000 to 0x1FFFFFFF), DCode (Data and debug accesses to 0x00000000 to 0x1FFFFFFF), System interface (instruction fetches, and data and debug accesses, to, 0x20000000 to 0xDFFFFFFF and 0xE0100000 to 0xFFFFFFFF) and Private Peripheral Bus(data and debug accesses to external PPB space, 0xE0040000 to 0xE00FFFFF). The internal PPB interface provides access to ITM, DWT, FPB ,SCS, MPU, NVIC. The external PPB interface provides access to TPIU, ETM, ROM and implementation-specific areas of the PPB memory map. 

I have converted these hexadecimals of Code memory space to decimals and binary in the following table : 

1.3 Programmer's Model

There are 13 GPR(R0-R12), stack pointer, link register and program counter.

Program status is reported in APSR, which has flag bit fields of negative condition,zero condition, Carry condition,Overflow condition, Q-bit and it can also have Greater than or Equal flags for SIMD instructions.

The Thumb instructions are executed as 16-bit and 32-bit halfword. If bits [15:11] of halfword are either 0b11101 or 0b11110 or 0b11111, then the halfword is the first halfword of a 32-bit instruction, else it is a 16-bit instruction. 

When register reads 0b11111, it means either reading the PC value or word-aligned PC value or zero. But for register write, it means either PC is destination register of an LDR or discarding the result or instruction is a memory hint instead of a load operation

When register reads 0b1101, the support for 32-bit Thumb instruction SP[1:0], which is SBZP (RAZ/WI), is restricted and it uses the same R13 register. 

The System Control Space, 0xE000E000 to 0xE000EFFF,  supports PID registers; general control and configuration; system handler; SysTick;  NVIC; fault status and control registers; PMSAv7; cache and branch predictor control; processor debug.

1.3.1 Program Status Register (PSR), special-purpose program status register

Source : ARM

On exception entry and exit, processor writes to IPSR(Interrupt Program Status Register), which can be read by MRS instruction.

The T bit of EPSR (Execution Program Status Register) executes Thumb instructions, when this Tbit is set to 1, and an overlaid ICI or IT field which supports interrupt-continue load/store instructions and the IT instruction. When used as ICI bits,  an interrupted exception-continuable multi-cycle load or store instruction information is revealed. When used as IT bits,   context information for the conditional execution of a sequence of instructions in an IT block, gets provided.

1.3.2 Special-purpose mask registers - PRIMASK, BASEPRI, FAULTMASK

1.3.3 Special-purpose CONTROL registers

• nPRIV, bit[0]
• SPSEL, bit[1]
• FPCA, bit[2]

1.3.4 Reserved special-purpose register bits - RAZ/WI

1.4 Memory Protection Unit

It uses a single, flat address space of  232=4294967296,   8-bit bytes from 0 to 232−1, the word-aligned address  A consists of the four bytes with addresses A, A+1, A+2, and A+3.

Source : ARM

1.5 Exceptions

Exceptions wiz., Reset, Non Maskable Interrupt, HardFault, MemManage, BusFault, UsageFault, DebugMonitor, 

SVCall and interrupts are supported by Cortex M4F.

• Reset : Power-on reset  and Local reset.

• Non Maskable Interrupt, NMI is permanently enabled with a fixed priority of -2. 

• HardFault is the generic fault that exists for all classes of fault that cannot be handled by any of the other exception mechanisms.

• MemManage handles memory protection faults.

• BusFault handles memory-related faults, other than those handled by the MemManage.

• UsageFault handles non-memory related faults.

• DebugMonitor is a synchronous exception.

• Supervisor Call, SVCall  handles the exception caused by the SVC instruction.

• Interrupts - Cortex M4F supports two system-level interrupts - PendSV and SysTick, and up to 496 external interrupts.

PendSV is used for software-generated system calls. SysTick is permanently enabled, and is controlled using ICSR.PENDSTSET and ICSR.PENDSTCLR.

1.6 Data Watch, DWT

DWT contains four configurable comparators 
• hardware watchpoint
• an ETM trigger
•  PC sampler event trigger
• data address sampler event trigger.

1.7 FPU

The Floating Point (FP) extension has versions- FPv4-SP and FPv5, supporting single-precision (32-bit)arithmetic, as either 32 single-precision or 16 double-precision registers. FPv5 has additional support for double-precision (64-bit) arithmetic. The FPv4-SP is only a variant of VFPv4-D16 extension of the ARMv7-A and ARMv7-R.

FP extension register bank can be accessed as either 

• Thirty-two 32-bit single-precision registers, S0-S31.
• Sixteen 64-bit double-precision registers, D0-D15.

The mapping between the registers is as follows:
•  S<2n> maps to the least significant half of D<n>
•  S<2n+1> maps to the most significant half of D<n>.

1.7.1 Floating-point Status and Control Register, FPSCR

FPSCR is defined in REGSEL[6:0] of the Debug Core Register Selector Register, DCRSR. Setting the FZ bit, FPSCR[24], enables flush-to-zero mode.

1.7.2 Floating Point Context Control Register, FPCCR, 0xE000EF34

FPCCR holds control data for FPU.

1.7.3 Floating Point Context Address Register, FPCAR, 0xE000EF38

FPCAR holds the location of the unpopulated FPRS allocated on an exception stack frame.

1.7.4 Floating Point Default Status Control Register, FPDSCR, 0xE000EF3C

FPDSCR holds the default values for the FP status control data that the processor assigns to FPSCR when it creates a new floating-point context.

1.8 Debug

For debug accesses, Advanced High-performance Bus Access Port (AHB-AP) interface is used. The external Debug Port (DP) can access using either SWJ-DP (Serial Wire JTAG Debug Port) or 2-pin SW-DP(Serial Wire Debug Port).

Source : ARM

1.9 Nested Vectored Interrupt Controller

The Nested Vectored Interrupt Controller, NVIC controls power management and facilitates low-latency exception and interrupt handling. NVIC supports up to 240 interrupts each with up to 256 levels of priority.

Used for Wake-up Interrupt Controller (WIC), Wait For Interrupt (WFI), Wait For Event (WFE) and the Send Event (SEV).

Source : ARM

2. SAM E51 Architecture

The SAM E51 Curiosity Nano Evaluation Kit has 32-bit  ATSAME51J20A microcontroller with 64-pins.

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2.1 Architecture

The Cortex M4F is based on ARMv7E-M architecture explained in the previous section, however, the previous section highlights the general Cortex M4F features and there are minor differences when it come to SAM E51 like NVIC supports up to 240 interrupts each with up to 256 levels of priority but SAM E51 supports 138 interrupts with eight different priority levels. 

The System Level Interface uses AMBA(Advanced Microcontroller Bus Architecture) technology to provide high-speed, low-latency memory accesses. The data endianness is Little-endian.

The Cortex M Cache Controller, CMCC provides L1 cache and using Tightly Coupled Memory (TCM), part of the cache can used. The cache size is determined by CFG.CSIZESW. CMCC has programmable monitor/32-bit counter which counts the number of clock cycles, the number of data hit or the number of instruction hit.

Source :Microchip

2.2 Power Supply

The power supply pins are 

• VDDIO powers I/O lines, XOSCn and the internal regulator for VDDCORE. The voltage is 1.71V to 3.63V.
• VDDIOB powers I/O B lines.  The voltage is 1.71V to 3.63V.
• VDDANA powers I/O lines, the Automatic Power Switch, ADC0/1, AC, DAC and PTC. The voltage is 1.71V to 3.63V.
• VBAT powers the Automatic Power Switch. The voltage is 1.71V to 3.63V.
• VDDCORE  powers the VSW core power domain and the VDDBU backup domain,memories, peripherals, DFLL48M, FDPLL200M, and RAMs.  the voltage is 1.2V.
• Automatic Power Switch is a configurable switch that selects between VDD and VBAT as supply for the internal output VSWOUT.

2.3 Oscillator Controller, OSCCTRL

OSCCTRL has one DFLL48M, two 8-48 MHz XOSC,  two DPLL which can output 96 MHz to 200 MHz  frequency. DFLL48M can operate in both open-loop mode and closed-loop mode. XOSCn can operate with an external clock or crystal oscillator.

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2.4 Memory

Source of the image gallery : Microchip

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2.5 Clock

The SAME51 clock system consists of oscillators, Generic Clock Controller(Generic Clock Generators and Generic Clocks) and Main Clock Controller.

Source of the image gallery : Microchip

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Generic Clock Controller (GCLK) generates, controls and distributes the asynchronous clock. The Generic Clock Generator 0 generates GCLK_MAIN, which is used by the Power Manager and the Main Clock (MCLK) module, which in turn generates synchronous clocks. Generic Clock 0 serves as the clock source for the DFLL48M clock input. The Generic Clock Generator 1 uses the DFLL48M as its clock source and feeds into Peripheral Channel 7. The Generic Clock 7(GCLK_SERCOM0_CORE) is connected to Serial Communication Interfaces SERCOM0. 

Synchronization Busy (SYNCBUSY) register is used to check if a sync operation is in progress for synchronization of clocks from different clock sources and/or with different clock speeds. Write-Synchronization is triggered by writing to a register in GCLK.

The synchronization delay, D :  (5*P_GCLK  + 2 * P_APB ) < D < (6 *P_GCLK + 3 * P_APB )

GCLK features 12 Generic Clock Generators [11:0] which provide GCLK_PERIPH up to 64 Peripheral Channels and CLK_MAIN. Each GCLK_GEN can be set to run from one of eight different clock sources except GCLK_GEN[1], which can be set to run from one of seven sources. MCLK generates system clocks with prescaler from 1x to 128x division. The CLK_MAIN is divided by an 8-bit prescaler. By default, the synchronous clocks run on the undivided main clock.

fCPU=fmainCPUDIV​.

2.5.1  What has to be Configured to Enable a Peripheral

• Clock Source
• Clock from Generic Clock Generator 
• Peripheral Channel that provides the Generic Clock signal to the peripheral 
• The user interface of the peripheral needs to be unmasked in the Power Manager.

T_{start_max} = Clock source startup time + 2 × clock source periods + 2 × divided clock source periods
T_{start_min} = Clock source startup time + 1 × clock source period + 1 × divided clock source period
T_{stop_min} = 1 × divided clock source pIeriod + 1 × clock source period
T_{stop_max} = 2 × divided clock source periods + 2 × clock source periods

Once the power has stabilized and the internal Reset is released, by default, SAM E51 run at 48MHz from DFLL48M.

2.6 Watch Dog Timer, WDT

When enabled, WDT run in active mode , is asynchronous and runs from a CPU-independent clock source. It will continue operation and issue a system reset or interrupt even if the main clocks fail. A 1.024 kHz oscillator clock is required to clock the WDT internal counter.  WDT recovers from error situations such as runaway code, by issuing a Reset. In Normal mode operation, there are 12 possible WDT time-out periods, selectable from 8ms to 16s.

2.7 Real-Time Counter, RTC

The RTC is a 32-bit counter with a 10-bit programmable prescaler which allows wide range of resolutions and time-out periods.

If clock source is 32.768kHz,

• minimum counter tick interval is 30.5μs,
• time-out periods can range up to 36 hours.
• maximum time-out period >  136 years (for counter tick interval of 1s)

2.7.1 Modes 

• Mode 0 - COUNT32: RTC serves as 32-bit counter
• Mode 1 - COUNT16: RTC serves as 16-bit counter
• Mode 2 - CLOCK: RTC serves as clock/calendar with alarm functionality

2.8 DMAC

2.9 Interrupts

Each peripheral can have many interrupt flags. Depending on criticality, the interrupt requests for one peripheral are either ORed together on system level, generating one interrupt or directly connected to an NVIC interrupt lines.

External pins,EXTINT[15..0] can beconfigured as interrupt lines using EIC( External Interrupt Controller) which has a configurable filter to remove spikes, clocked by GCLK_EIC or by CLK_ULP32K.

Source : Microchip

2.10 CAN

2.11 USART

2.12 I2C

2.13 SPI

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2.14  Debug

The I/O pins  PA30 is pull-up enabled and configured as input for debugging purpose. SAM E51 hasdebug support level 3 which means full debug plus DWT data matching.

The trace support level is 2.

2.15 USB

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2.16 Reset Controller

The Reset Controller (RSTC) manages the reset of the microcontroller.

Source : Microchip

On any Reset the synchronous clocks start to their initial state. On a User Reset the GCLK module starts to its initial state, except for Generic Clocks that are write-locked.

On a Power-on Reset, the 32KHz clock sources are reset and the GCLK module starts to its initial state. After a power-on Reset, the RSTC is enabled and the Reset Cause (RCAUSE) register indicates the POR source.