In this lab we will enable PS DMA engine to improve data flow between PL-based BRAM and external DDR3 memory.
We will base on project from lab 5. We need to launch SDK. Then we need to check if in system.hdf there is present BRAM IP block.
Now please create a new application project with empty application. Then we need to import test application called: dma_test.c provided in course materials.
Now we could program FPGA device and launch on hardware.
There is a simple application which allow to test improvements in data transfer with usage of DMA. I do not why by during choosing option 1 BRAM to BRAM transfer the application hangs. It always stops in this method: Xil_DataAbortHandler. I am using the Vivado in version 2018.2 but source file is for 2017.4, so maybe there are some differences in configuration ?
Update:
I found the reason of this issue. It was wrong Interconnect IP type. I choosed AXI SmartConnect instead of a AXI Interconnect. Here is output after correction:
