Name: TI/WE Webinar Series: Designing the Power Stage for a Simple Buck Application
Start: 2016-02-25T15:00Z
End: 2016-02-25T16:00Z

Watch the Entire Webinar Series

{tabbedtable} Tab Label	Webinar
About This Webinar	In this webinar you can expect to learn: The right switching frequency according to input voltage. Power expect loop bandwidth by switching frequency, gain bandwidth of E/A, output filter Inductor selection by windings losses DC/AC, core losses and core geometry Semiconductor selection by switching losses, conducted losses driver losses, forward losses Output capacitor selection by ripple stress and dynamic requirements Designing a RC snubber to reduce radiated emissions at VHF band
About the Presenter	Bernd Geck, Texas Instruments Systems Applications Manager for Power Design Services Europe Bernd Geck is heading the European Power Supply Design Services Team based in Freising, Germany. He holds a Diploma in Electrical Engineering from the University of Applied Sciences in Ulm and has more than two decades of experience in electronic hardware design with a focus on power management and RF. Bernd and the Power Supply Design Services team generate over 200 designs per year. Bernd educated hundreds of customers in power supply design at various seminars and workshops across Europe and Northern America. He has held the TI Power Supply Design Seminars as presenter all over Europe since 2008
Live Giveaway	After each webinar there is a quiz related to the respective session with 2 questions. For this session members can win: Analog Engineer's Pocket Reference Members who complete all four quizzes correctly will also be entered for a chance to win: Wireless Power Transfer Solution Kit To GO Terms and Conditions are Attached.
Webinar Recording	You don't have permission to edit metadata of this video. Edit media Dimensions x Subject (required) Brief Description Tags (separated by comma) Video visibility in search results Parent content Poster Upload Preview

Thank you Herve. Bernd has answered this question already. Best regards

…typically at Germany; sometimes Austria/Switzerland/BeNeLux and Nordic,
best regards, Bernd

Where is your TI power Workshop ?

Dear Ramon Hernandez Marti

Here are TI' replies:

- Slide 5: 0.67 mA rms current seems
plausible, however 0.1 W divided by (0.67)^2 is NOT equal to 0.111 but 0.222.

2% overall losses at the FET, so 50mW
switched lossed and 50mW conducted losses for a balanced and most efficient
approach;

the conducted losses are diddipated at
drain-source-channel, 50mW/.67W^2 = 111mW

- Slide 6: On the second equation the power 2 seems to apply to the current
unit only. Parentheses are needed. (also, the result is 21.55 which should
round to 21.6)

conducted losses: Pcond = Irms^2 x RdsON

- Slide 7: the duty cycle actually used
is not 42% but the more exact value 41.666 (= 5/(16+8)/2)

for nonsync topology the true value
is even bigger, (Vout+Vf)/(Vin+Vf), so for 500mV diode drop 44%;

visit my TI Power Workshop, there I’m
doing a deep dive – here I got 45mins only…

- Slide 9: Under "Input Capacitors'
it says "use the same amount". Amount of what? Capacitance? Then 9 x
22µF capacitors are needed, not 2. Does it refer to the same charge V x C? In
this case 4 x 22µF are needed

depending on source impedance and line
impedance regarding reflected ripple = conducted emmissions;

1* 22uF/25V/X7R/1210 are fully
sufficient to handle ripple stress 670mArms;

but to pass some agency approvals even
more low impedant input capacitance or an additional EMI input filter might be
needed

- Excellent slide 17!

- Slide 20: The picture shows a large
electrolytic capacitor besides the ceramic ones detailed on slide 9. Is this
Cin on slide 19?

yes, added a bulk capacitor at the input
to provide a low source impedance, followed by filter inductor, followed by
input caps;

left and right of inductor 100nF for
attenuating RF spikes further; this EMI input PI-filter lowers reflected ripple

- The input filter is only hinted, however it could ring which would influence
the frequency compensation and make the circuit unstable. Are you covering
input filters in the upcoming presentations?

sorry, type 3 loop compensation (here
ctrl. works in voltage mode) is only affected by LC OUTPUT filter;

set input filter LC corner frequency to
1/10 of Fsw, provides in theory attenuation of -40dB to fundamental;

effective around -30dB due to
interwindings capacitance and cross talking;

visit my TI Power Workshop, there I’m
doing a deep dive and a hands on regarding loop compensation

Top Comments

jwatson over 9 years ago +3

Dear All Apologies for the technical difficulties today connecting you with our presenter. We were unable to share the panellists screen on this occasion. We will be rescheduling or sharing a recording…
Former Member over 9 years ago +1

Come on, element14Dave ! We're all getting a bit anxious now.
Former Member over 9 years ago +1

Your mic isn't muted "bless you"

rscasny over 8 years ago in reply to Former Member

a
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jwatson over 9 years ago in reply to Former Member

Thank you Herve. Bernd has answered this question already. Best regards
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jwatson over 9 years ago in reply to Former Member

…typically at Germany; sometimes Austria/Switzerland/BeNeLux and Nordic,
best regards, Bernd
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Former Member over 9 years ago in reply to jwatson

Where is your TI power Workshop ?
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jwatson over 9 years ago in reply to Former Member

Dear Ramon Hernandez Marti

Here are TI' replies:

- Slide 5: 0.67 mA rms current seems
plausible, however 0.1 W divided by (0.67)^2 is NOT equal to 0.111 but 0.222.
2% overall losses at the FET, so 50mW
switched lossed and 50mW conducted losses for a balanced and most efficient
approach;
the conducted losses are diddipated at
drain-source-channel, 50mW/.67W^2 = 111mW

- Slide 6: On the second equation the power 2 seems to apply to the current
unit only. Parentheses are needed. (also, the result is 21.55 which should
round to 21.6)
conducted losses: Pcond = Irms^2 x RdsON
- Slide 7: the duty cycle actually used
is not 42% but the more exact value 41.666 (= 5/(16+8)/2)
for nonsync topology the true value
is even bigger, (Vout+Vf)/(Vin+Vf), so for 500mV diode drop 44%;
visit my TI Power Workshop, there I’m
doing a deep dive – here I got 45mins only…
- Slide 9: Under "Input Capacitors'
it says "use the same amount". Amount of what? Capacitance? Then 9 x
22µF capacitors are needed, not 2. Does it refer to the same charge V x C? In
this case 4 x 22µF are needed
depending on source impedance and line
impedance regarding reflected ripple = conducted emmissions;
1* 22uF/25V/X7R/1210 are fully
sufficient to handle ripple stress 670mArms;
but to pass some agency approvals even
more low impedant input capacitance or an additional EMI input filter might be
needed

- Excellent slide 17!
- Slide 20: The picture shows a large
electrolytic capacitor besides the ceramic ones detailed on slide 9. Is this
Cin on slide 19?
yes, added a bulk capacitor at the input
to provide a low source impedance, followed by filter inductor, followed by
input caps;
left and right of inductor 100nF for
attenuating RF spikes further; this EMI input PI-filter lowers reflected ripple

- The input filter is only hinted, however it could ring which would influence
the frequency compensation and make the circuit unstable. Are you covering
input filters in the upcoming presentations?
sorry, type 3 loop compensation (here
ctrl. works in voltage mode) is only affected by LC OUTPUT filter;
set input filter LC corner frequency to
1/10 of Fsw, provides in theory attenuation of -40dB to fundamental;
effective around -30dB due to
interwindings capacitance and cross talking;
visit my TI Power Workshop, there I’m
doing a deep dive and a hands on regarding loop compensation
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TI/WE Webinar Series: Designing the Power Stage for a Simple Buck Application

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