Thank you for this nice and helpful introduction to the MiniZed ecosystem.
There seems to be a lot of magic going on in the IP integration part. While I certainly understand the benefits of such a graphical approach to system design (throwing in IP blocks and having the IP integrator wire everything together), I'm worried about Vivado trying to "dumb it down" for me to a point where I can't really figure out what's going on at the system level anymore (not even considering RTL-level of course).
Take the example in the second half of the presentation for instance; here's what I can gather:
1. it all starts with a vanilla, unconfigured Zynq block,
2. then block automation is run, the vanilla Zynq block gets reconfigured so that it matches the MiniZed-specific model,
3. two IP blocks (AXI I2C and AXI UART controllers) get instanciated on the PL side,
4. connection automation is run, ports to the "outside world" get added to the design,
5. then, ports are created on the PS side, so that it can master the I2C and UART blocks through the AXI interface,
6. finally, connection automation is run again, and boom, out of nowhere, 2 extra IP blocks get added to the design.
What are these two extra blocks ? I suspect they are clock domain crossing FIFOs, but you can't really make out the labels from the low-res video capture.
Besides, I suspect the IP integrator is not just about wiring up blocks together, right ? Surely there must be a lot going on behind the scenes (updates to the AXI configuration, clock tree configuration, etc..).
So yeah, that's great that we don't *have* to be exposed to all these things, but I'm sure many of us (system architects, maybe even hobbyists) would gladly work their way up through all this, in order to get a proper sense of control over their design, and beef up their expertise on the Zynq. Let me say it again: there's a lot of automation and magic going on here, and I don't feel so comfortable with it.
Is it still possible to get access to some clear-text configuration files (or even better: HDL code) that was generated along the way by the IP integrator, in order to make sense of what was done ? Ideally some sort of text files, something that can be compared and versioned up into a git repository for better integration in existing workflows.
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