Xilinx Workshop: Getting to Know Vivado Series with Adam Taylor

The Vivado Design Suite from Xilinx offers tools and methodologies to speed up FPGA development, while improving productivity. Within Vivado, developers can leverage C-based design, capture, simulate and implement programmable logic designs targeting Xilinx FPGA and SoCs (System-on-Chips).

This three-session introduction to Xilinx Vivado Design Suite will examine how we capture designs in Vivado using both RTL entry and IP Integrator. Following design capture we will examine Vivado’s simulation capabilities that help ensure the performance of the captured design aligns with requirements. When we reach the desired functional performance level, we will move on to design implementation and programming file creation for deployment.

Just as with real life, our journey does not end there. We will also explore how we can debug the implemented design on the device as it is integrated into the wider system, should the need occur.

Each workshop session will walk you through everything you need to know to go from a Zero to a Hero using Vivado. Adam Taylor will walk you through everything you need to know to get started using Vivado. Like the previous PYNQ course we will provide examples, and as the series progresses build onto what we've learned. No board is required.

Dates and Register for Free:

Workshop:	Dates and Register:
Session 1 - Getting to Know Vivado Pt 1 In this session we will get an overview and introduction to Vivado, key elements of FPGA design, and the different views inside Vivado and what they can be used for. Topics covered include: FPGA flow – RTL -> Synthesis -> Place and Route -> Bitstream What do we use Vivado for? What is its role in FPGA and SoC Development? Design entry in Vivado -> RTL View Simulation -> XSIM (Vivado RTL Simulation) Implementation Flow -> Synthesis View, Implementation, Bit Stream	Wednesday, 26th of August 2020 10:30 CT / 3:30 PM GMT Xilinx Workshop: Getting to Know Vivado Part I
Session 2 - Getting to Know Vivado - Part II In this session we will look more closely at more commonly used features which enable designs to be generated faster. Topics covered include: IP Integrator – Reduce the RTL you need to write and accelerate your design Constraints – What is there role in the design, how do we use them? Timing Analysis – What is timing closure, why is it important, and how do we achieve it? Programming Configuration Memories	Wednesday, 2nd of Sept 2020 10:30 CT / 3:30 PM GMT Xilinx Workshop: Getting to Know Vivado Part II
Session 3 - Getting to Know Vivado - Part III In this session we will introduce advanced concepts, such as creating our own custom IPs, debugging on hardware, working with configuration control, and scripting in Vivado. Topics covered include: Creating custom IP using AXI interfaces Debugging in Vivado – ILA, VIO insertion Working with softcore processors – MicroBlaze example Configuration control and scripting	Wednesday, 9th of Sept 2020 10:30 CT / 3:30 PM GMT Xilinx Workshop: Getting to Know Vivado Part III

Workshop:

Dates and Register:

Session 1 - Getting to Know Vivado Pt 1

In this session we will get an overview and introduction to Vivado, key elements of FPGA design, and the different views inside Vivado and what they can be used for.

Topics covered include:

FPGA flow – RTL -> Synthesis -> Place and Route -> Bitstream
What do we use Vivado for? What is its role in FPGA and SoC Development?
Design entry in Vivado -> RTL View
Simulation -> XSIM (Vivado RTL Simulation)
Implementation Flow -> Synthesis View, Implementation, Bit Stream

Wednesday, 26th of August 2020

10:30 CT / 3:30 PM GMT

Xilinx Workshop: Getting to Know Vivado Part I

Session 2 - Getting to Know Vivado - Part II

In this session we will look more closely at more commonly used features which enable designs to be generated faster.

Topics covered include:

IP Integrator – Reduce the RTL you need to write and accelerate your design
Constraints – What is there role in the design, how do we use them?
Timing Analysis – What is timing closure, why is it important, and how do we achieve it?
Programming Configuration Memories

Wednesday, 2nd of Sept 2020

10:30 CT / 3:30 PM GMT

Xilinx Workshop: Getting to Know Vivado Part II

Session 3 - Getting to Know Vivado - Part III

In this session we will introduce advanced concepts, such as creating our own custom IPs, debugging on hardware, working with configuration control, and scripting in Vivado.

Topics covered include:

Creating custom IP using AXI interfaces
Debugging in Vivado – ILA, VIO insertion
Working with softcore processors – MicroBlaze example
Configuration control and scripting

Wednesday, 9th of Sept 2020

10:30 CT / 3:30 PM GMT

Xilinx Workshop: Getting to Know Vivado Part III

Presenter:

Founder and Lead Engineer, Adiuvo Engineering & Training Ltd

Adam has over 18 years engineering experience of which a significant number of these are at Design Authority / Responsible Engineer level on complex System and Electronic projects for advanced satellite payloads, safety critical systems (SIL4) and other high performance systems. He is both a Chartered Engineer and Fellow of the IET, as well as, a prolific blogger on technical subjects such as Electronics design, FPGA design and Reliable techniques.He is also the author of the MicroZed Chronicles, a weekly blog which focuses on the Xilinx Zynq & Zynq UltraScale+ SoC, as well as, the Vivado and SDSoC tool sets. The series contains over 250 in depth technical articles, providing examples and how to's which cover every aspect of using the device from basics to advanced concepts such as Asymmetric Multi Processing and High Level Synthesis.