That is what I'm planning. This is just the beginning. I was just starting where I was. I first thing I want to get accomplished is to get memory working and a serial terminal working so I can play around with it. This project will probably never be complete, but just further along . There is a lot of things I want to do but have to take it in steps. This weekend I want to get status LEDs set up. Reading and writing from memory, write an archaic is and watch what it can do. Then upgrade and upgrade from there.
Was doing some thinking .I have transceivers between the CPU and the address and data buses. Is it necessary to have transceivers between the memory and the buses, since memory will almost always be involved in most of the bus usage, ie. Dma.? Dreams like there should not be too much draw on the bus keeping memory on it. The chips are only enabled when memory is being called for anyhow. They do you think?
That is what I'm planning. This is just the beginning. I was just starting where I was. I first thing I want to get accomplished is to get memory working and a serial terminal working so I can play around with it. This project will probably never be complete, but just further along . There is a lot of things I want to do but have to take it in steps. This weekend I want to get status LEDs set up. Reading and writing from memory, write an archaic is and watch what it can do. Then upgrade and upgrade from there.
Was doing some thinking .I have transceivers between the CPU and the address and data buses. Is it necessary to have transceivers between the memory and the buses, since memory will almost always be involved in most of the bus usage, ie. Dma.? Dreams like there should not be too much draw on the bus keeping memory on it. The chips are only enabled when memory is being called for anyhow. They do you think?
Adding transceivers and buffers is a usual task for Z80 older designs when we used to use TTL.
The decision to use them depends upon the Z80 variant used.
I think the original NMOS variant can only handle IOL=+2mA and IOH--250uA (1 TTL or 4 LS loads) whereas the CMOS variant IOL=+2mA and IOH=-1.6mA so ensure your design does not exceed these fanout limits.
If you plan to use DRAM with DMA, you'll need to ensure that all bus masters continue to refresh the DRAM but I'm guessing you'll be using SRAM.
