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What’s the worst mistake/problem you’ve made during a project, and what did you learn from it? We are asking e14 in our Join, Share & Win Competition

E14Alice

Hello Everyone!

Hope you are all doing well. I’m excited to announce that this month's AskE14 question is: What is the worst mistake or problem you've encountered during a project, and what did you learn from it?

Sharing your experiences can help others identify similar challenges and understand how to overcome them. I hope this discussion will be beneficial for those who are just starting out on a project or feeling stuck with a problem.

Here's the question:

What’s the worst mistake/problem you’ve made during a project, and what did you learn from it? 

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Competition Details

You'll have to be a member of the element14 Community to join in and take part in this “Join, Share & Win” challenge. It's simple, all you have to do is:

1. You need to make sure you are Register  or Login
2. Then answer the following question by adding a reply or commenting!

What’s the worst mistake/problem you’ve made during a project, and what did you learn from it?  

The Community team will then select the best 3 answers to win a Raspberry Pi 400!

This month, we are giving away:

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Learn more

Terms and Conditions 

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Winners 

  

 

 

 will be in touch shortly regarding the prize 

Parents

  • Back in the early 80's when we were first learning to design 6 and 8 layer PCBs and we had limited ERC and DRC rules,  I made a critical current density error in a PCB design.  We were doing high power and high performance designs where we used power and ground planes for power distribution and impedance control.  I had a design that was using a coplanar waveguide for critical signal delivery.  I had instructed the PCB designer to stitch the coplanar and bottom ground planes together with closely spaced vias.  The waveguide worked great,  but because this was before the use of blind vias, I had inadvertently perforated a high power trace that ran below the bottom ground plane.  Our existing ERC/DRC checks passed.  Of course, the design powered up and checked out fine, but after several hours of operation - the board went up in flames.  It was extremely fortunate that I was there when it happened and was able pull the PCB from the backplane before the system caught fire.  

    After that I always made sure that I checked power and ground film for via perforation to identify and fix areas that would have high current density.  Years afterward we had a DFM group that helped check for these types of errors and many others that I hadn't considered.  I've had other less dramatic failures that were mitigated by DFM.  When we first started designing our own custom ICs, a hard lesson that we had to learn was to match the TCEs between the PCB and component substrates.  Not doing that caused reliability failures due to attachment failures.

Reply

  • Back in the early 80's when we were first learning to design 6 and 8 layer PCBs and we had limited ERC and DRC rules,  I made a critical current density error in a PCB design.  We were doing high power and high performance designs where we used power and ground planes for power distribution and impedance control.  I had a design that was using a coplanar waveguide for critical signal delivery.  I had instructed the PCB designer to stitch the coplanar and bottom ground planes together with closely spaced vias.  The waveguide worked great,  but because this was before the use of blind vias, I had inadvertently perforated a high power trace that ran below the bottom ground plane.  Our existing ERC/DRC checks passed.  Of course, the design powered up and checked out fine, but after several hours of operation - the board went up in flames.  It was extremely fortunate that I was there when it happened and was able pull the PCB from the backplane before the system caught fire.  

    After that I always made sure that I checked power and ground film for via perforation to identify and fix areas that would have high current density.  Years afterward we had a DFM group that helped check for these types of errors and many others that I hadn't considered.  I've had other less dramatic failures that were mitigated by DFM.  When we first started designing our own custom ICs, a hard lesson that we had to learn was to match the TCEs between the PCB and component substrates.  Not doing that caused reliability failures due to attachment failures.

Children