Back in the early 80's when we were first learning to design 6 and 8 layer PCBs and we had limited ERC and DRC rules,  I made a critical current density error in a PCB design.  We were doing high power and high performance designs where we used power and ground planes for power distribution and impedance control.  I had a design that was using a coplanar waveguide for critical signal delivery.  I had instructed the PCB designer to stitch the coplanar and bottom ground planes together with closely spaced vias.  The waveguide worked great,  but because this was before the use of blind vias, I had inadvertently perforated a high power trace that ran below the bottom ground plane.  Our existing ERC/DRC checks passed.  Of course, the design powered up and checked out fine, but after several hours of operation - the board went up in flames.  It was extremely fortunate that I was there when it happened and was able pull the PCB from the backplane before the system caught fire.  

After that I always made sure that I checked power and ground film for via perforation to identify and fix areas that would have high current density.  Years afterward we had a DFM group that helped check for these types of errors and many others that I hadn't considered.  I've had other less dramatic failures that were mitigated by DFM.  When we first started designing our own custom ICs, a hard lesson that we had to learn was to match the TCEs between the PCB and component substrates.  Not doing that caused reliability failures due to attachment failures.

Back in the early 80's when we were first learning to design 6 and 8 layer PCBs and we had limited ERC and DRC rules,  I made a critical current density error in a PCB design.  We were doing high power and high performance designs where we used power and ground planes for power distribution and impedance control.  I had a design that was using a coplanar waveguide for critical signal delivery.  I had instructed the PCB designer to stitch the coplanar and bottom ground planes together with closely spaced vias.  The waveguide worked great,  but because this was before the use of blind vias, I had inadvertently perforated a high power trace that ran below the bottom ground plane.  Our existing ERC/DRC checks passed.  Of course, the design powered up and checked out fine, but after several hours of operation - the board went up in flames.  It was extremely fortunate that I was there when it happened and was able pull the PCB from the backplane before the system caught fire.  

After that I always made sure that I checked power and ground film for via perforation to identify and fix areas that would have high current density.  Years afterward we had a DFM group that helped check for these types of errors and many others that I hadn't considered.  I've had other less dramatic failures that were mitigated by DFM.  When we first started designing our own custom ICs, a hard lesson that we had to learn was to match the TCEs between the PCB and component substrates.  Not doing that caused reliability failures due to attachment failures.

It would be easy to make this kind of mistake in this day and age as well.  Thanks for sharing.