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Programable Gain Amplifier

scottiebabe

I have a project where I am in need of a amplifier with digitally adjustable gain.

There are many ways to construct a variable gain amplifier, one solution involves using a digital potentiometer in the negative feedback path around an op-amp.

A simplified schematic is shown below

image

Image sourced from Application note: ww1.microchip.com/.../01316A.pdf

The closed loop gain of the amplifier is now a function of the digiPOT’s wiper position:

image
Table for an 8-bit digiPOT, table 12 for a 7-bit device is full of mistakes

Half of the wiper codes map to closed loop gains between 1 and 2. There isn’t a lot of choice for larger gains after a gain of 64 then next available choice is 128.

Pretty Neat! I don’t happen to need more than 20 kHz of bandwidth, so finding an op-amp with a gain-bandwidth product greater than 20kHz*128 = 2.6 MHz is not a problem.

Breadboard

It just so happens I have some digital potentiometers laying around.
Specifically, the Microchip MCP4131 digital POT, which has 7-bit resolution and a total ladder resistance of 10k.

https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/22060b.pdf

I also have some Renesas ISL28291 dual-opamps.

Both have been sent to me by element14 (and the cool breadbroad, thanks element14!)

I tossed them onto a breadboard and used a RPI pico to interface with the MCP4131 (github.com/.../main)

image


Just like a rotary potentiometer the digiPOT has 3 terminals: A, B, W

image

Instead of a having a continuous resistance track and a movable wiper contact, the digi pot has 128 small resistors in a series string and an analog mux that can select any of the 129 tap points.

If you apply a fixed potential across the A and B terminals, then with the wiper to set to mid-scale code, the output voltage is half the input. At a wiper code of 0, ideally the wiper voltage should be 0 (unfortunately due to the resistance of the terminal disconnect switch it slightly greater than 0).

User beware, behavior at the extreme tap-points is worse than advertised.

At a wiper code of 127, I measured a gain of 80x instead of the ideal value of 128x. Disappointing.

There also isn’t a lot of ‘gain resolution’, the previous wiper code of 126 provides an ideal gain of 64x.

Compounding 2 for more gain and resolution

To achieve a higher total gain and have more gain steps to choose from, I put 2 in series.

image

Now with 2 stages, there are 5363 unique gain values.

image

The vast majority of the unique gains are below 50 dB. Above 50 dB there are 55 unique gain values.

Here is a scopeshot of the PGA cycling between a gain of 1 and 6

image

The brief excursion on the scope plot is python being slow, micropython takes its sweet time between the spi write of the first and second digiPOT.

image

In summary, I am pretty happy with the dynamic range of the amplifier. The amplifier can be programed to provide gains of anywhere between unity and 10000x with 20 kHz of bandwidth and an input referred noise of approximately 3nV/rootHz.

Not bad for parts I had laying around. All the big name semi’s have PGAs with lower noise and more bandwidth all integrated within a single IC for reasonable prices. So, if you need one, you can shop around for a pre-engineered solution. 

Parents

  • I am very interested in ultra-low noise opamps. I might plug this circuit into LTspice to see if the INOISE really lands close to 3nV/rtHz.

  • in reply to wolfgangfriedrich

    I took the exact circuit into LTspice and did a input referred noise simulation. Just replace the digi-pot with a pair of coupled resistors and a step list of parameters.
    image
    With resistors away from maximum gain, the minimum noise is around 4.6 nV/rtHz (-166 dBV/rtHz) at 70 kHz, which is pretty good. At the datasheet standard frequency of 1 kHz it is still 7.9 nV/rtHz (-159 dBV/rtHz).
    image
    The very minimum of the noise happens when one opamp is at maximum gain and the noise contribution of the opamp becomes negligible. 1.8 nV/rtHz (-175 dBV/rtHz) at 90 kHz. 

    At lower frequencies, the noise gets worse quickly. It is really difficult to get good noise performance at frequencies < 20 Hz. Audiophiles/fools might not care, but scientists do. It is usually a J-FET + low noise opamp combination with really big caps at the bias and reference voltages. Other components are noisy too, especially resistors. And the supply rail will contribute as well. 
    This was fun. 

    PS: I don't see how I can add attachments to comments; to share my LTspice sources. Any helpful hints?

  • in reply to wolfgangfriedrich

    This is wonderful!

    As you say the first amplifier largely defines the effective noise figure of the full circuit. When I created the gain and pot code LUT, when possible I chose codes that maximized the gain of the first op-amp.

    At lower gains, the input referred noise increases, but with less gain the total output noise decreases. So if you imagine a gain being chosen to level the output to 1 Vrms, the SNR improves.

    One reference point to consider is the PGA2505

    image

    It's a PGA with 60 dB of adjustable gain and has the following integrated input referred noise

    image

    Which is about 500nVrms (over 20 kHz of bandwidth) at the maximum gain setting. As the input signal gets larger and requires less gain the noise figure and final SNR improves

    image

    The bottom line is the noise limit (4vrms is cheating, 500 nVrms gained up by 60 dB is 500 uVrms on the output or an snr of -66 dB referenced to a 1Vrms output)

    The schematic I posted has a 1.6 kHz HPF on the input, so the input referred noise below that frequency gets worse because the input referred noise is the noise on the output divided gain (below 1.6kHz the amplifier is rejecting not amplifying).

Reply
  • in reply to wolfgangfriedrich

    This is wonderful!

    As you say the first amplifier largely defines the effective noise figure of the full circuit. When I created the gain and pot code LUT, when possible I chose codes that maximized the gain of the first op-amp.

    At lower gains, the input referred noise increases, but with less gain the total output noise decreases. So if you imagine a gain being chosen to level the output to 1 Vrms, the SNR improves.

    One reference point to consider is the PGA2505

    image

    It's a PGA with 60 dB of adjustable gain and has the following integrated input referred noise

    image

    Which is about 500nVrms (over 20 kHz of bandwidth) at the maximum gain setting. As the input signal gets larger and requires less gain the noise figure and final SNR improves

    image

    The bottom line is the noise limit (4vrms is cheating, 500 nVrms gained up by 60 dB is 500 uVrms on the output or an snr of -66 dB referenced to a 1Vrms output)

    The schematic I posted has a 1.6 kHz HPF on the input, so the input referred noise below that frequency gets worse because the input referred noise is the noise on the output divided gain (below 1.6kHz the amplifier is rejecting not amplifying).

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