What beginners mistakes have I made?

Things you might consider:

1) use a ground plane on the lower (non component side) of the baord.

2) keep all the components on one side (if you will hand solder a couple of prototypes this doesn't matter but for production it always costs more to populate both sides.)

3) don't ever make sharp V shapes with track - it causes problems in etching

4) try to take tracks out of sm components on axis and the same for all

5) you have some very thin tracks and some tiny vias - you don't need to use such aggressive design rules a board like this.

MK

Michael,

I agree with all of your statements. Can you explain better your #4 advice?

Hi S D,

Basically it means that whatever the orientation of the component (typically they are at zero or 90 degrees orientation to each other and the board edges), then ideally the traces out of the pads of the component should be placed at these angles too, i.e. if you start at the pad of a component, then preferably the trace from it should be routed at zero or 90 degrees too, and not at some other angle. Once the trace is a distance away from the component pad, then it can be routed at a different angle if desired.

Not sure how important this is, but the FT230X documentation calls for 27 ohm resistors inline on on the D+ and D- lines.  Also, I am not sure that on the FT230X, that the VCC pin should be tied to the VCCIO and 3V3OUT pins.  Power should be connected to VCC (with a 0.1uF bypass cap to ground) and VCCIO, RESET and 3V3OUT should be connected together with another 0.1uF cap to ground.  I would also add a diode between the power jack and the regulator for reverse power protection.

Good luck with your project!

Gene

Thanks Shabaz,

I'm wrestling with a switch chip that doesn't want to talk to an FPGA so a bit pushed for time today.

MK

Thanks Michael

AD 3. Thanks - I haven't realized that one - the explanations I read was about current flow which is why I tried to kept angles for flow <45°.

AD 4. Sorry - I have no clue what you mean.

AD 5. I use default 6 mils for signals and for power/ground signals that supply a lot of components I choose 20. I'm not sure what to choose if default are not correct - obviously the thinner the track the less conductivity it has and I know I could calculate in principle the resistance but probably there are some good rules of thumb.

It might be worth increasing the trace width to the power pins on the USB connector...

Do you care to elaborate on #1? why no GND plane on the components side of the board ?

Luis

Hi Maciej,

Its easiest if you can find some example physical PCBs, and examine them closely, to see patterns to follow.

Here is an example.

Position 1 is a pad belonging to an IC. You can see that the trace marked 2 comes off at a nice angle (zero degrees) before it bends at position 3.

Similarly, look at the pad marked 4. This belongs to a surface mount resistor or capacitor. Again, the trace comes off at a nice angle (zero degrees) before it gets bent near position 5, and then disappears off into a via shown in green.

Similarly, position 6 shows a capacitor. Here the trace comes off at 90 degrees before it bends at any other angle.

Now look to position 7. This is a through-hole pad for a dual-in-line header, like you are using in your design. Here there was not enough room to easily come off at zero or 90 degrees, so 45 degrees was used, but exactly through the centre of the pad, as if the pad were a clock face, and the trace was one of the clock hands, starting at the centre of the pad. In other words, don't bring a trace to a through-hole pad in a way that the trace and pad together look like a music note (or golf club) shape combined.

Also, 6 mil is unnecessary for your design. The example PCB below is more dense than yours, and all the visible traces are nearly all 10mil (with a few that are 8mil, you can just about see the difference widths if you look closely). There are no 6mil traces here.

I would also add that the example added by shabaz shows some very good examples of spacing between traces.  When possible, leave ample spacing between traces as this reduces potential interference between signals.  In your design, near the GPIO connector and also the JTAG connector, a lot traces bunch up together.  You could move each trace further from the others and produce a clearer (aesthetically and electronically) board.  Layout is sort of an art and a science, mixed together.

Gene