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Legacy Personal Blogs High Throughput SPI traffic part 0 - Buffers and Parallel Data Lines
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  • Author Author: Jan Cumps
  • Date Created: 13 May 2016 3:47 PM Date Created
  • Views 1254 views
  • Likes 6 likes
  • Comments 9 comments
  • texas_instrutments
  • spi
  • mibspi
  • buffered spi
  • hercules
  • launchpad
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High Throughput SPI traffic part 0 - Buffers and Parallel Data Lines

Jan Cumps
Jan Cumps
13 May 2016

We know SPI as a 4*-wire protocol. But it doesn't have to be.

I'm checking high speed SPI data transfer with buffers, DMA and parallel data lines.

 

image

 

While I'm at it, I'm also going to test hardware handshaking with the Enable signal. Let's see if we can get decent speed.

High Throughput Requirements

 

SPI (Serial Peripheral Interface) as a serial protocol can be reasonable fast.

In its purest form, where we have bidirectional traffic, the limits are set by the speed of the clock and the speed at which source and destination can provide and consume data.

For many sensors, common SPI with low frequencies s good enough to exchange data.

That changes when we're trying to talk to displays and other peripherals that need big data.

 

There are mechanisms that we can deploy to deal with throughput inside our microcontroller.

We can use DMA and interrupts, so that the handling of the traffic can be done in parallel with other microcontroller tasks.

That frees up the processor to collect or create the required data, while its SPI module handles traffic independently.

If we apply this method in a right way, we can in many cases take care that the communication buffer has enough data to keep the throughput high.

 

image

But that still leaves us with the limits of how many bits you can rush through a single data line.

The clock is telling how many single bits we ca bump onto the traffic track.

The industry has come up with a solution that breaks the one bit per tick paradigm: multiple data lines.

That may be odd, because the name of the protocol indicates it's serial, and multiple data lines are parallel.

If that bothers you , you can call it PPI and live happy ever after.

 

High Throughput Goals

 

In this blog series, Ill try to get 50 Mbits per second transferred through the SPI interface.

The hardware that I have available has DMA, SPI memory buffers and 4 data lines for MISO and MOSI.

Theoretically, based on the maximum SPI clock rate my controller can have, I should get 80 Mbits.

 

The SPI clock is 20 MHz. I have 4 data lines, so 4 bits per clock cycle: 80 Mbits /s

 

Reality will also play a role. It 'll be tough to prepare and consume actual data at that rate.

The test bed will do everything to keep our SPI buffers full enough to achieve an as-close-to-theoretical throughput as possible.

50 Mbits is a good 60% efficiency. Let's see if we can achieve that...

 

* there's also 3-wire possible

 

The Series
0 - Buffers and Parallel Data Lines
1a - Buffers and DMA
1b - SPI without Buffers
2 - SPI with Buffers
3a - SPI with DMA
3b - SPI with DMA works
4a - SPI Master with DMA and Parallel Data Lines
Hercules microcontrollers, DMA and Memory Cache

>

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Top Comments

  • balearicdynamics
    balearicdynamics over 7 years ago +1
    Very useful and interesting article! I am just exploring the best way to connect a PSoC 4 with MSP432 via ISP or I2C (one of the two alternatives) and this represent a good starting point. Enrico
  • shabaz
    shabaz over 7 years ago in reply to Jan Cumps +1
    Complex topics are great to read when they are well written : ) I thought it was very clear to follow!
  • balearicdynamics
    balearicdynamics over 7 years ago +1
    A great starting depicting a fascinating scenario. I like it ! Enrico
  • Jan Cumps
    Jan Cumps over 7 years ago

    The fifth part is up, with DMA added to the mix

     

    image

     

    High Throughput SPI traffic part 3a - SPI with DMA

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  • Jan Cumps
    Jan Cumps over 7 years ago

    I just learned, by clicking on the  link in peteroakes' comment,

    that SPI with 4 data lines is called Quad-SPI: SPI Storm – Advanced information – Byte Paradigm – Speed up embedded system verification

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  • Jan Cumps
    Jan Cumps over 7 years ago in reply to Jan Cumps

    #4 is the first time that I add buffers to the recipe.

    From 400 µs to less than 120 µs to draw a line.

     

    High Throughput SPI traffic part 2 - SPI with Buffers

     

    image

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  • Jan Cumps
    Jan Cumps over 7 years ago

    Part 3 is still unbuffered SPI. But I've got all things set up to be buffer ready.

    I now also know that the LCD is compatible with buffered SPI. I can blast a whole line of pixels in one time.

    Speed gain: From more tha 2ms per line to less that 400 µs.

     

    High Throughput SPI traffic part 1b - SPI without Buffers

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  • balearicdynamics
    balearicdynamics over 7 years ago

    A great starting depicting a fascinating scenario. I like it !

     

    Enrico

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