Group Actions
Engagement
  • Author Author: Jan Cumps
  • Date Created: Date Created
  • Views 4921 views
  • Likes 6 likes
  • Comments 20 comments
Related
Recommended

Hercules microcontrollers, DMA and Memory Cache

Jan Cumps

DMA and memory cache don't always play nicely together.

I had an issue when trying to use serial communication and DMA on a TI Hercules controller. The DMA data wasn't appearing in my read buffers.

TI's application specialists helped me to resolve my issues. It was related to ARM memory cache settings.

I've written a step-by-step guide on the hackster.io forum on that subject.

 

 

Due to the subject, this hasn't turned into an easy-to-read novel. I hope it may help fellow developers struggling with similar issues.

 

When you're playing with DMA, you think everything is working ok, and you don't see any data written to your variables, this post may be worth looking into.
It's based on an SCI example, but applicable in many DMA situations.

 

Default Cache configuaration is write-back:

image

For DMA relevant buffers, you can specify a chunk of RAM with write-through configuation.

image

There's more to do than just setting aside a portion of the memory. Check the video for a quick overview, and the hackster.io blog post for a step-by-step explanation with a working project attached.

 

The Series
0 - Buffers and Parallel Data Lines
1a - Buffers and DMA
1b - SPI without Buffers
2 - SPI with Buffers
3a - SPI with DMA
3b - SPI with DMA works
4a - SPI Master with DMA and Parallel Data Lines
Hercules microcontrollers, DMA and Memory Cache

  • Hi, 
    Thanks for this blog, where I found a clear-cut explanation on Cache coherence with DMA.

    I could not be able to find the link for 4b which is a continuation of this blog, can you please share that link.

    Kind Regards, 
    Naveen

  • in reply to DAB

    The DMA controller pulls 4 * 16 bits in one go from RAM per time.

    The DMA controller is autonomous across 64 values. It will do 64 /4 = 16 reads from RAM to get those 64 values, and 64 writes to the SPI buffer - without eating clocks from the main MCU..

    Then it stops until 2 actions happen: the main microcontroller has provided 64 new values, and the slave pulls the Enable line low (meaning it has the bandwidth to consume a next burst of 64).

     

    edit: I'm writing a blog that goes into detail on what happens from when the CPU hands off to the DMA controller.

  • in reply to Jan Cumps

    Ok, so you get four 16-bit values in one DMA pull from memory, which is more efficient than pulling them one at a time.

     

    It will make the SPI transfer mostly transparent, unless you are moving a lot of data over your SPI busses.

     

    DAB

  • in reply to Jan Cumps

      wrote:

     

       wrote:

     

    Hi Jan,

    ...

     

    No rush on testing. As I have said before, I used to analyze computer architectures and have found many instances where DMA devices had more affect on the CPU than advertised.

     

    DAB

    My curiosity is triggered. It's also a chance to get better at working with DMA on these controllers - I'm particularly bad at it.

     

    I've been able to port a TI example to the controller that I have, but it does not work. Not a single bit comes out of the SPI controller.

    I've created a ticket over at ti: https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/736834

    The ticket at the TI E2E community is solved and I have that speedy mechanism working now:

     

    • reads 64 16-bit values from RAM in chunks of 64 bits in DMA (4 values in a single read),
    • then writes these in chunks of 16 bits to SPI buffer (maximum write size. DMA controller does the folding from 64 to 16)
    • 4 parallel SPI output lines to send 4 bits per clock tick - this is called parallel pin mode (or Quad mode in some documents for this 4-pin setup). The receiver has to support this. The Hercules supports up to 4 parallel SPI pins in and out.

     

    Here's a capture.Every CS block clocks away 64 16-bit values and checksum/parity info.

    Only SIMO 0 and 2 are captured by the logic analyser in the image below. I did not connect 1 and 3.

    image

     

    image

  • in reply to DAB

      wrote:

     

    Hi Jan,

    ...

     

    No rush on testing. As I have said before, I used to analyze computer architectures and have found many instances where DMA devices had more affect on the CPU than advertised.

     

    DAB

    My curiosity is triggered. It's also a chance to get better at working with DMA on these controllers - I'm particularly bad at it.

     

    I've been able to port a TI example to the controller that I have, but it does not work. Not a single bit comes out of the SPI controller.

    I've created a ticket over at ti: https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/736834