The series will use high-voltage FETs in half-bridge configuration. This time I look at the bridge's output signal.
I'm particularly interested in the overshoot, because controlling that is one of the claimed advantages of GaN technology. |
The high and low side of the bridge are controlled by an opposite signal. Both signals have a dead time inserted when one signal goes low and the other switches high.
GaN semiconductors don't need a lot of dead time. The setup here is configured for a 50 ns band.
*1: I was sloppy when capturing this scope window. The falling edge of the input signal should be where the orange line is. Check comments below for more info.
Thank you jc2048 for spotting this.
The scope capture above shows the input (low-power) signals.
The white line is the input signal, with 22% duty cycle and a frequency of 200 kHz.
The yellow line is the driver signal for the high side FET, the blue signal for the low side one. Check the schematic below to get an idea of where the 3 signals occur.
(excuses for the mismatch in scope horizontal scale setting between yellow and blue. I only saw this after I disconnected my setup. They have the same amplitude.)
I'm going to probe the switcher's output signal. I'll zoom in on the overshoot positions, so you can see that the signal is behaving decently in the dead time.
This trace is a full high part of the output at 200 kHz, 22% duty cycle.
It gives an impression of the switching artifacts just before the edges.
A detailed capture of the rising edge overshoot looks like this:
The input signal is 60 V. The overshoot is approximately -8 V:
On the falling edge, there's less switching residue:
(the time scale is extended to the limits of what I can show on my scope screen. Check the full signal above to get an idea of how steep (50 ns) this ramp-down and overshoot is.)
The evaluation board that I'm using has reasonable filtering at the output. Let's check how the DC signal after that flter looks like.
The load I'm using is approx. 12 W (12 V, 1 A). The capture below shows only the AC (noise) component of the output.
I get close to 650 mV of ripple peak-to-peak.
Not surprisingly, the largest artifacts appear at the edges of the PWM driver signals. This is a reasonable DC signal.
Further filtering will smoothen it more - the board I'm using is to show how the GaN FETs perform, so it doesn't focus on output filtering.
| Part 1: Several 100 Volts |
| Part 2: Test Setup with LMG3410 Half-Bridge |
| Part 3: Probing the LMG3410 Half-Bridge |
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