Now if it were an inverted PNP then the base would have to be biased with a voltage divider (using the 'Duino PS) and the input analog signal could be capacitively coupled to the base.
The electrons flow from negative to positive in all three.
1. from the N (emitter) to the P (base)
2. Power Supply One.
3. 'Duino Ground to 'Duino +5V
The only down side to the given circuit is that the analog input will only ever see a max. voltage of 3.6 V.
Now if it were an inverted PNP then the base would have to be biased with a voltage divider (using the 'Duino PS) and the input analog signal could be capacitively coupled to the base.
The electrons flow from negative to positive in all three.
1. from the N (emitter) to the P (base)
2. Power Supply One.
3. 'Duino Ground to 'Duino +5V
The only down side to the given circuit is that the analog input will only ever see a max. voltage of 3.6 V.
