I am trying to connect the AU15 board to a PC via the PCIe interface. I have followed the tutorial in the documentation but I cannot get the root complex to enumerate the FPGA as an endpoint.
PCIe example:
www.hackster.io/.../perfecting-pcie-with-auboard-8cabd5
I have several doubts:
1. In the tutorial and in the board configuration files (previously exported to Vivado), the PCIe clock reference is listed as 100MHz, but the documentation (AUBoard-15P Development Kit Hardware User Guide Version 1.4) indicates that it is 125MHz.
2. On the other hand, the IP cores associated with the PCIe interface (XDMA, AXI-PCIe bridge) use a different pin assignment than the documentation (implying lane reversal).
3. It is indicated that the default lane size selection is 4-lane (J22 pins 2 and 3, shunted), but by default there is no jumper connected.
I have requested the schematics from our FAE. Once we have them, I assume we will be able to resolve these issues, but as this is urgent, I would like to know if anyone knows the answer to these questions.
Thank you. Best regards.