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AUBoard 15P PCIe interface is not working

dgfernandez

I am trying to connect the AU15 board to a PC via the PCIe interface. I have followed the tutorial in the documentation but I cannot get the root complex to enumerate the FPGA as an endpoint.

PCIe example:
www.hackster.io/.../perfecting-pcie-with-auboard-8cabd5

I have several doubts: 

1. In the tutorial and in the board configuration files (previously exported to Vivado), the PCIe clock reference is listed as 100MHz, but the documentation (AUBoard-15P Development Kit Hardware User Guide Version 1.4) indicates that it is 125MHz.

2. On the other hand, the IP cores associated with the PCIe interface (XDMA, AXI-PCIe bridge) use a different pin assignment than the documentation (implying lane reversal).

3. It is indicated that the default lane size selection is 4-lane (J22 pins 2 and 3, shunted), but by default there is no jumper connected.

I have requested the schematics from our FAE. Once we have them, I assume we will be able to resolve these issues, but as this is urgent, I would like to know if anyone knows the answer to these questions.

Thank you. Best regards.

  • 0

    Hello,

    It sounds like you have the problem in hand, but on the issue of lane selection, I faced that when working with the LiteFury PCIe board.  The PCIe XDMA Bridge core selected lanes different from how the board is wired.  I handled it with reset_property and set_property commands in my compilation script.  Here is a link to what I did.

    https://github.com/hdlguy/litefury_pcie/blob/main/x4_pcie/implement/compile.tcl

    The PCIe interface worked perfectly in the end.

  • 0
    Looking over my description, I don't think my questions are clear. Let me explain further.
    We are trying to connect the AUboard-15p to a PC via the PCIe interface. We have followed the "Perfecting PCIe with AUBoard" tutorial from hackster.io but we cannot get the root complex to enumerate the FPGA as an endpoint.  While reviewing the documentation(AUBoard-15P Development Kit Hardware User Guide Version 1.4), we noticed some inconsistencies:
     
    PCIe:
    1. In the tutorial and in the board configuration files (previously exported to Vivado), the PCIe clock reference is listed as 100MHz, but the documentation  indicates that it is 125MHz. In any case, we have tested both without success. Really, what clock frequency should be used?
    2. The IP cores associated with the PCIe interface (XDMA, AXI-PCIe bridge) use a different pin assignment (extracted from board configuration files) than the documentation (implying lane reversal, lane[3]=lane[0], lane[2]=lane[1],lane[1]=lane[2],lane[0]=lane[3] ). We have assigned the pins manually, but we have not been able to enumerate the board from the host either. We have tried both assignments, but I would like to know which is the correct pin assignment.
    We have also tried disabling ASPM in the BIOS host, but the lspci command does not return anything related to the FPGA.
     
    We have seen in the errata document that there were some problems with some capacitors in the PCIe interface of this revision of board, so we have also implemented PCIe Gen2 (instead of Gen3 or Gen4), but the problems are the same.
     
    Can anyone provide us with the code for a PCIe basic example to ensure that our AUboard-15p is not faulty?
     
    Jumpers:
     
    Also, we have some questions about jumpers. 
    1. J46. Which value should we select? There is no information about this in the documentation.
    2. What are the allowed values for jumper J22(lane configuration)?

    Thank you in advance.

    Best regards.

  • 0 in reply to padudle

    Thank your for your quick response. 

    In our tests, we used two different pin assignments.


    1. The one provided by XDMA by default.
    2. The one indicated in the documentation.

    The method we followed is different from the one you indicated. We set the value to True in the XDMA configuration wizard in the Disable GT Channel Loc Constraint field (GT settings tab) and then provided the corresponding pinout through a constraints file. We have verified that the pin assignment changes were successful by reviewing the results after implementing the design.

    In any case, thank you for your response and for suggesting a different method to the one we use.

    Best regards.

  • 0 in reply to dgfernandez

    The PCIe core in Vivado generates the incorrect GT mapping for the GT Quad.

    There is a check box in the core generation to override the defaults such that your XDC can map it properly.

    You can look at the Vivado IO reports to verify the mapping of lanes is 1:1 and not swapped because of the core.

    As far as the PCIe REFCLK, that is supposed to be 100MHz for PCIe. It’s an error in the User guide that needs to get corrected.

  • 0 in reply to iksevas

    I strongly disagree with your first statement - its the opposite, the board engineers did not respect the required lane mappings. Everybody buying AMD/Xilinx FPGAs and/or development boards would by default expect the vendor IPs such as XDMA or QDMA to work with default configuration. This thread clearly highlights whats the expected configuration without any doubt.

  • 0 in reply to iksevas

    Knowing that the reference clock is 100MHz (not 125MHz as indicated in the User Guide  "AUBoard-15P Development Kit Hardware User Guide Version 1.4") and that the pins are those indicated in the User Guide (different from those used by Vivado IP cores), we have generated a project with the UltraScale+ Integrated Block for PCI Express that works correctly using PCIex4 Gen4. We have also got the AXI-PCIe Bridge to work correctly. We have our own DMA core, so we are not interested in XDMA functionality and will not be testing it.


    In summary, in case it helps anyone else with the same problem:

    1. J22 pins 2 and 3 must be shunted to select 4x lane size selection. This is indicated as the default setting in the documentation, although in our case no jumper was connected.

    2. The PCIe clock reference is 100MHz.

    3. The pinout shown in Table 7 of "AUBoard-15P Development Kit Hardware User Guide Version 1.4" must be used.  For this purpose, set the Disable GT Channel Loc Constraint field (GT settings tab) value to True in the XDMA or Integrated Block For PCIe configuration wizard and then provided the corresponding pinout through a constraints file. 

    Note: If you use the example design from the integrated block for PCIe wizard, all pins generated automatically by Vivado are incorrect, including reference clocks and reset pins.

    Thank you all.

  • 0 in reply to Aenerine

    I worded that improperly. My apologies. The board is wired differently than the example IP. The beauty of the flexibility of  FPGAs. I’m glad the end-user was able to be successful with the board and the IP used.