I am mapping LVDS signals whiah are routed to bank 66/86 of FPGA. I am using LVDS IO standard of LVDS_18 as per the reference user_constarints.xdc file available in the following link
https://www.avnet.com/americas/products/avnet-boards/avnet-board-families/auboard-15p-fpga-development-kit/
But vivado - v.2024.2 tool is indicating this as a critical warning mentioning unknown IO standard.
Should we ignore this warning or proceed with tool suggested IO standard?
