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Zedboard PL and PS Boot Asynchronously

embedded_guy

Hi,

 

I'm trying to optimize my boot time on my system (currenlty using a Zynq zedboard).

 

I have an image booting from QSPI that runs the FSBL and then FreeRTOS. I created another image that included the bitstream, but this increased the load time by 10x.

 

I was wondering if there was a way to boot the PL independently, so that the FSBL does not load the bitstream. A way to have the PL load it's own bitstream asynchronously without the PS doing anything.

 

Any help is appreciated.


Thanks.

  • I do not have an example, but you can load the boot.bin without a PL image, then in parallel load the PL image post OS boot.

     

    --Dan

  • in reply to drozwood90

    Thanks for the response, Dan.

     

    I am trying to see if the PS can load in parallel at the same time as the PL load. It's not clear if the PS is needed to control the QSPI interface or if that can be done without PS involvement.

     

    I want to understand how the Zynq can be configured to download a bitstream and init the PS and PL in parallel. To speed up the load, I don't want the PS involved in the PL configuration stage.

  • in reply to embedded_guy

    Hi there,

     

    Zynq is a processor first design, so it would need to be loaded first in all cases.

    Even if you do not want the processor running, you still need to have a bare metal design that loads into the PS before the PL can be loaded up (I've done this when I was working on some accelerator testing where I did not need the PS to be involved).

     

    --Dan

  • in reply to drozwood90

    Thanks, Dan. Seems the TRM indicates it can be separately configured, but guess not.

     

    I'm seeing a loading time of the bitstream of about 1.5 seconds which seems really slow. Not sure why it's so slow loading the bitstream on the zedboard. Or if it can be speeded up.

  • in reply to embedded_guy

    HI there,

     

    I was thinking on this, and seeing that no one has responded beyond my reply, have you tried to ask this same question over at the Xilinx forums or your local FAE?  The FAES tend to have better information on corner cases like this.  Over at the Xilinx forums, you might find someone that has already done this.  I'm not saying you WILL get an answer, but at the very least, you might get some path forward to play around.  I do know that there are things you can do to speed up the boot time, but I'm not sure what the path is for that.

     

    --Dan