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LVDS Differential Clock to Single Ended

cybero

Hi, I'm using the Zynq Mini-Module Plus.

This board comes with a LVDS clock. Taking a look at the XDC provided by AVNET we can see:

 

## 200MHz System Clock

set_property LOC F14 [ get_ports CLK_N]

set_property IOSTANDARD LVDS [ get_ports CLK_N]

 

 

set_property LOC F15 [ get_ports CLK_P]

set_property IOSTANDARD LVDS [ get_ports CLK_P]

So, I wonder how can I convert this LVDS clock into a single ended clock because I've never seen this before. I've always worked with FPGA with single ended clocks so I'm a bit lost on this now.

 

Thanks in advance for the help.

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  • Hi Salvador,

     

    Keep in mind that once any signal enters the FPGA, there is no more differential signals; everything is single ended. However, outside the FPGA (whether input or output) differential signals can be/are used whenever the signals are at higher frequncies for reasons like signal integrity, etc

     

    I haven't looked at the schematic of Zynq MMP, but from the XDC file, it looks like this is your system input clock. Since it is a differential clock, it is being given on a differential pin pair. However, inside the IO block in your FPGA where these are getting connected, these will be converted from differential to single ended clock, and most probably drive a clock region, and after that you don't need to worry about differential clocks...everything is single ended inside. Hope it helps you understand.

     

    Best Regards,
    Saad I. Tiwana

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  • Hi Salvador,

     

    Keep in mind that once any signal enters the FPGA, there is no more differential signals; everything is single ended. However, outside the FPGA (whether input or output) differential signals can be/are used whenever the signals are at higher frequncies for reasons like signal integrity, etc

     

    I haven't looked at the schematic of Zynq MMP, but from the XDC file, it looks like this is your system input clock. Since it is a differential clock, it is being given on a differential pin pair. However, inside the IO block in your FPGA where these are getting connected, these will be converted from differential to single ended clock, and most probably drive a clock region, and after that you don't need to worry about differential clocks...everything is single ended inside. Hope it helps you understand.

     

    Best Regards,
    Saad I. Tiwana

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