Actions
Forum Thread Details
  • Replies 2 replies
  • Subscribers 347 subscribers
  • Views 486 views
  • Users 0 members are here
Related

Xilinx HLS error

nnills

Hi,

 

I recently bought a minized board. When building the example 24*24 multiply example in SDSoC I encountered this error:

 

Moving function mmult_hw to Programmable Logic

ERROR: [SdsCompiler 83-5031] Problem detected in Vivado HLS run - unable to find solution implementation directory for mmult_hw D:/FPGA/SDSOC_proj/Bentest2/Debug/_sds/vhls/mmult_hw/solution/impl/ip. For possible causes, review D:/FPGA/SDSOC_proj/Bentest2/Debug/_sds/vhls/mmult_hw_vivado_hls.log.

D:/FPGA/SDSOC_proj/Bentest2/Debug/_sds/vhls/mmult_hw_vivado_hls.log (last 20 lines):

INFO: [HLS 200-435] Setting 'config_sdx -target' configuration: config_export -vivado_optimization_level=0

INFO: [HLS 200-435] Setting 'config_export -vivado_optimization_level' configuration: config_export -vivado_phys_opt=none

INFO: [HLS 200-435] Setting 'config_sdx -target' configuration: config_rtl -module_auto_prefix=1

INFO: [HLS 200-435] Setting 'config_sdx -target' configuration: set_clock_uncertainty 27%

INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 2.7ns.

WARNING: [HLS 200-483] The 'config_rtl -prefix' command is deprecated and will be removed in a future release. Use 'config_rtl -module_prefix' as its replacement.

INFO: [SCHED 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.

INFO: [HLS 200-10] Analyzing design file 'D:/FPGA/SDSOC_proj/Bentest2/src/mmult_accel.cpp' ...

Error in linking the design.

    while executing

"source D:/FPGA/SDSOC_proj/Bentest2/Debug/_sds/vhls/mmult_hw_run.tcl"

    invoked from within

"hls::main D:/FPGA/SDSOC_proj/Bentest2/Debug/_sds/vhls/mmult_hw_run.tcl -l mmult_hw_vivado_hls.log"

    ("uplevel" body line 1)

    invoked from within

"uplevel 1 hls::main {*}$args"

    (procedure "hls_proc" line 5)

    invoked from within

"hls_proc $argv"

INFO: [Common 17-206] Exiting vivado_hls at Sun Dec  6 16:08:50 2020...

 

I looked into it and found these two threads by mdouglas:

Error building U96_avnet Matrix Multiply Project | Zedboard

https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/SDSoC-build-project-failed/td-p/889988

 

In both however he explains how it may have something to do with the antivirus, but has no solution. I thought that now, nearly 3 years after those posts, there might be more insight into the problem. Does one of you know how this could be solved?

I am using Windows 10; Vivado(SDSoC, HLS, SDK)2019.1.

 

Thanks in advance, Nils

  • Hi Nils,

     

    Of all the Avnet SOMs and SBCs, the MiniZes has the least amount of programmable logic (PL).  I suspect this may be what your SDSoC issue might be.  You may be running out of Zynq PL resources to fit a 24x24 matrix multiply.  I know that we at Avnet have struggled to fit this and other Vitis and SDSoC designs into the MiniZed PL. 

     

    --Tom

  • HI there,

     

    the 24x24 should fit as long as you do not have anything else in the design.  Based on the error you are seeing, it does seem like your build environment.

    Are you rebuilding the exact image that was provided?  Can you try using the VirtualBox environment that we suggest?  It seems like you are trying to build this under Windows.  Windows has a file depth limit.  As is suggested in the Avnet training materials, you might want to try to build a clean copy of the design in "D:/Bentest2" instead of "D:/FPGA/SDSOC_proj/Bentest2"

     

    --Dan