Hello Everybody,
I have created a MIPI image processing pipeline design and built a Petalinux project using zedboard, FMC pcam adapter and Pcam .
The objective is to save the image on the SD card at 720P resolution. The Vivado design can be seen in the Image
I am using v2019.1 of vivado and Petalinux.
I was successfully able to stream video with the similar design using bare-metal application. 
During the boot I et the following error
| Header 1 |
|---|
xilinx-video amba_pl:video_cap: device registered xilinx-csi2rxss 43c00000.mipi_csi2_rx_subsystem: Xilinx CSI2 Rx Subsystem device found! xilinx-video amba_pl:video_cap: Entity type for entity 43c00000.mipi_csi2_rx_subsystem was not initialized! xilinx-video amba_pl:video_cap: Entity type for entity 43c10000.v_demosaic was not initialized! xilinx-demosaic 43c10000.v_demosaic: Xilinx Video Demosaic Probe Successful xilinx-vtc 43c40000.v_tc: device found, version 6.010 |
The status log mipi csi2 rx subsystem is the as seen below
| Header 1 |
|---|
43c00000.mipi_csi2_rx_subsystem: ================= START STATUS ================= 43c00000.mipi_csi2_rx_subsystem: ***** Core Status ***** 43c00000.mipi_csi2_rx_subsystem: Short Packet FIFO Full = false 43c00000.mipi_csi2_rx_subsystem: Short Packet FIFO Not Empty = false 43c00000.mipi_csi2_rx_subsystem: Stream line buffer full = false 43c00000.mipi_csi2_rx_subsystem: Soft reset/Core disable in progress = false 43c00000.mipi_csi2_rx_subsystem: ******** Clock Lane Info ********* 43c00000.mipi_csi2_rx_subsystem: Clock Lane in Stop State = true 43c00000.mipi_csi2_rx_subsystem: ******** Data Lane Info ********* 43c00000.mipi_csi2_rx_subsystem: Lane SoT Error SoT Sync Error Stop State 43c00000.mipi_csi2_rx_subsystem: 0 false false false 43c00000.mipi_csi2_rx_subsystem: 1 false false false 43c00000.mipi_csi2_rx_subsystem: 2 false false false 43c00000.mipi_csi2_rx_subsystem: 3 false false false 43c00000.mipi_csi2_rx_subsystem: ********** Virtual Channel Info ************ 43c00000.mipi_csi2_rx_subsystem: VC Line Count Byte Count Data Type 43c00000.mipi_csi2_rx_subsystem: 0 0 0 (null) 43c00000.mipi_csi2_rx_subsystem: 1 0 0 (null) 43c00000.mipi_csi2_rx_subsystem: 2 0 0 (null) 43c00000.mipi_csi2_rx_subsystem: 3 0 0 (null) 43c00000.mipi_csi2_rx_subsystem: 4 0 0 (null) 43c00000.mipi_csi2_rx_subsystem: 5 0 0 (null) 43c00000.mipi_csi2_rx_subsystem: 6 0 0 (null) 43c00000.mipi_csi2_rx_subsystem: 7 0 0 (null) 43c00000.mipi_csi2_rx_subsystem: 8 0 0 (null) 43c00000.mipi_csi2_rx_subsystem: 9 0 0 (null) 43c00000.mipi_csi2_rx_subsystem: 10 0 0 (null) 43c00000.mipi_csi2_rx_subsystem: 11 0 0 (null) 43c00000.mipi_csi2_rx_subsystem: 12 0 0 (null) 43c00000.mipi_csi2_rx_subsystem: 13 0 0 (null) 43c00000.mipi_csi2_rx_subsystem: 14 0 0 (null) 43c00000.mipi_csi2_rx_subsystem: 15 0 0 (null) 43c00000.mipi_csi2_rx_subsystem: ================== END STATUS ================== |
What am I doing wrong ?
Any help would be great .
I am attaching the device tree files and the boot log and the design pdf.
Thanks in Advance
| design_1.pdf | |
