I followed the instruction for petalinux and create the linux image and BOOT.BIN
$ petalinux-package --boot --fsbl <FSBL image> --fpga <FPGA bitstream> --uboot
The uart screen output
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
Xilinx First Stage Boot Loader
Release 14.6/2013.2 May 23 2014-09:08:31
Devcfg driver initialized
Silicon Version 3.1
Boot mode is SD
SD: rc= 0
SD Init Done
Flash Base Address: 0xE0100000
Reboot status register: 0x60600000
Multiboot Register: 0x0000C000
Image Start Address: 0x00000000
Partition Header Offset:0x000009C0
Partition Count: 3
Partition Number: 1
Header Dump
Image Word Len: 0x000F6EC0
Data Word Len: 0x000F6EBF
Partition Word Len:0x000F6EC0
Load Addr: 0x00000000
Exec Addr: 0x00000000
Partition Start: 0x000062C0
Partition Attr: 0x00000020
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFD14E8F
Bitstream
Encrypted
In FsblHookBeforeBitstreamDload function
PCAP:StatusReg = 0x40000A30
PCAP:device ready
PCAP:Clear done
Level Shifter Value = 0xA
Devcfg Status register = 0x40000A30
PCAP:Fabric is Initialized done
PCAP register dump:
PCAP CTRL 0xF8007000: 0x4E00E07F
PCAP LOCK 0xF8007004: 0x0000001A
PCAP CONFIG 0xF8007008: 0x00000508
PCAP ISR 0xF800700C: 0x0802000B
PCAP IMR 0xF8007010: 0xFFFFFFFF
PCAP STATUS 0xF8007014: 0x0006DA30
PCAP DMA SRC ADDR 0xF8007018: 0x00100001
PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF
PCAP DMA SRC LEN 0xF8007020: 0x000F6EC0
PCAP DMA DEST LEN 0xF8007024: 0x000F6EBF
PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF
PCAP MBOOT 0xF800702C: 0x0000C000
PCAP SW ID 0xF8007030: 0x00000000
PCAP UNLOCK 0xF8007034: 0x757BDF0D
PCAP MCTRL 0xF8007080: 0x30800100
DMA Done !
FPGA Done !
In FsblHookAfterBitstreamDload function
Partition Number: 2
Header Dump
Image Word Len: 0x0000EFC3
Data Word Len: 0x0000EFC3
Partition Word Len:0x0000EFC3
Load Addr: 0x3FC00000
Exec Addr: 0x3FC00000
Partition Start: 0x000FD180
Partition Attr: 0x00000010
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0x806D5CC5
Application
PartionLoadAddr 3FC00000 DDR_START_ADDR 00100000 DDR_END_ADDR 1FFFFFFF
INVALID_LOAD_ADDRESS_FAIL
FSBL Status = 0xA00F
This Boot Mode Doesn't Support Fallback
In FsblHookFallback function
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
The output
PartionLoadAddr 3FC00000 DDR_START_ADDR 00100000 DDR_END_ADDR 1FFFFFFF
indicates that load address is not in valid range.
My question is that DDR_START_ADDR and DDR_END_ADDR are defined in xparameters.h which was created by Xilinx SDK but how does petalinux determine the PartitionLoadAddr.
Thanks
