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PartitionLoadAddr is not in the range

Former Member

I followed the instruction for petalinux and create the linux image and BOOT.BIN

$ petalinux-package --boot --fsbl <FSBL image> --fpga <FPGA bitstream> --uboot

The uart screen output

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>


Xilinx First Stage Boot Loader

Release 14.6/2013.2     May 23 2014-09:08:31

Devcfg driver initialized

Silicon Version 3.1

Boot mode is SD

SD: rc= 0

SD Init Done

Flash Base Address: 0xE0100000

Reboot status register: 0x60600000

Multiboot Register: 0x0000C000

Image Start Address: 0x00000000

Partition Header Offset:0x000009C0

Partition Count: 3

Partition Number: 1

Header Dump

Image Word Len: 0x000F6EC0

Data Word Len: 0x000F6EBF

Partition Word Len:0x000F6EC0

Load Addr: 0x00000000

Exec Addr: 0x00000000

Partition Start: 0x000062C0

Partition Attr: 0x00000020

Partition Checksum Offset: 0x00000000

Section Count: 0x00000001

Checksum: 0xFFD14E8F

Bitstream

Encrypted

In FsblHookBeforeBitstreamDload function

PCAP:StatusReg = 0x40000A30

PCAP:device ready

PCAP:Clear done

Level Shifter Value = 0xA

Devcfg Status register = 0x40000A30

PCAP:Fabric is Initialized done

PCAP register dump:

PCAP CTRL 0xF8007000: 0x4E00E07F

PCAP LOCK 0xF8007004: 0x0000001A

PCAP CONFIG 0xF8007008: 0x00000508

PCAP ISR 0xF800700C: 0x0802000B

PCAP IMR 0xF8007010: 0xFFFFFFFF

PCAP STATUS 0xF8007014: 0x0006DA30

PCAP DMA SRC ADDR 0xF8007018: 0x00100001

PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF

PCAP DMA SRC LEN 0xF8007020: 0x000F6EC0

PCAP DMA DEST LEN 0xF8007024: 0x000F6EBF

PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF

PCAP MBOOT 0xF800702C: 0x0000C000

PCAP SW ID 0xF8007030: 0x00000000

PCAP UNLOCK 0xF8007034: 0x757BDF0D

PCAP MCTRL 0xF8007080: 0x30800100

DMA Done !

FPGA Done !

In FsblHookAfterBitstreamDload function

Partition Number: 2

Header Dump

Image Word Len: 0x0000EFC3

Data Word Len: 0x0000EFC3

Partition Word Len:0x0000EFC3

Load Addr: 0x3FC00000

Exec Addr: 0x3FC00000

Partition Start: 0x000FD180

Partition Attr: 0x00000010

Partition Checksum Offset: 0x00000000

Section Count: 0x00000001

Checksum: 0x806D5CC5

Application

PartionLoadAddr 3FC00000 DDR_START_ADDR 00100000 DDR_END_ADDR 1FFFFFFF

INVALID_LOAD_ADDRESS_FAIL

FSBL Status = 0xA00F

This Boot Mode Doesn't Support Fallback

In FsblHookFallback function

<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<


The output

PartionLoadAddr 3FC00000 DDR_START_ADDR 00100000 DDR_END_ADDR 1FFFFFFF

indicates that load address is not in valid range.

My question is that DDR_START_ADDR and DDR_END_ADDR are defined in xparameters.h which was created by Xilinx SDK but how does petalinux determine the PartitionLoadAddr.

Thanks

  • 0

    The Xilinx ZC702 board and the MicroZed each have 1 Gig of DDR memory which is assigned an address range of 00100000 to 3FFFFFFF. The ZedBoard only has half as much DDR memory and has an address range of 00100000 to 1FFFFFFF.  It looks like the hardware you generated (for a Zedboard?) does not match the Petalinux you generated or copied.

     

    What instructions did you follow to generate your linux image and boot.bin? Were you following the Avnet Petalinux Speedway lab instructions or something else?

     

    -Gary

  • 0

    Gary,

    My xparameters.h file says

    /* Definitions for peripheral PS7_DDR_0 */

    #define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000

    #define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF

    so it seems correct.

    I am using manual ug980-petalinux-board-bringup.pdf and when creating application project, I choose zed_hw_platform(predefined)as the hardware platform. I do get the error when I execute the command

    shashi@Zynq002:~/projects/zedboard01/zed_prj_bsp$ petalinux-config --get-hw-description -p ../zedlnx

    INFO: Checking component...

    INFO: Getting hardware description...

    INFO: Using MSS file /home/shashi/projects/zedboard01/zed_prj_bsp/system.mss and XML file /home/shashi/projects/zedboard01/zed_prj_bsp/../zed_hw_platform/system.xml

    INFO: Copy autoconfig for PetaLinux project: /home/shashi/projects/zedboard01/zedlnx

    ERROR: Only single-cpu PetaLinux OS type supported.

    ERROR: Failed to sync up hardware description!

    But I proceeded further anyway.

    Instead of using petalinux-package to create BOOT.BIN as I had done in my original mail, I decided to use bootgen with the appropriate load and start address


    the_ROM_image:

    {
        [bootloader]./zed_boot/Debug/zed_boot.elf

        ./zedlnx/images/linux/system.bit

        [load = 0x101000, startup = 0x101000]./zedlnx/images/linux/u-boot.elf

    }

    Note that this works correctly with windows ce but not with linux.



    Now, I don't get the error but the system hang, and do not proceed to execute the second stage boot loader


    Handoff Address: 0x00101000

    In FsblHookBeforeHandoff function

    SUCCESSFUL_HANDOFF

    FSBL Status = 0x1


    Looking at the code, I can see that the start address is not correct.

    So, I am asking how do sync the hw-description from my bsp to my project.

    How can I get hands on Avnet Petalinux Speedway lab ?

    Also, Is there a manual which can help me build the boot image directly from Xilinx source tree.



    Thanks



  • 0

    The Xilinx Petalinux wiki site should have all of the documents you need: http://www.wiki.xilinx.com/PetaLinux

     

    I am not sure why you installation is not working but you might try going back through the process to verify that you didn't miss a step somewhere.

     

    I think the Petalinux Speedways are still being held in some parts of the country: 

    http://www.em.avnet.com/en-us/design/trainingandevents/Pages/Xilinx-SpeedWay-Design-Workshops.aspx

     

    If you are unable to attend one live you can ask your local Avnet FAE for the material. We also plan to post the material on this site in the near future. The Avnet Petalinux labs do require either a ZedBoard or a MicroZed board as well as an Ubuntu Live USB stick with the files on it. 

     

    -Gary