Actions
Forum Thread Details
  • State Not Answered
  • Replies 4 replies
  • Subscribers 367 subscribers
  • Views 595 views
  • Users 0 members are here
Related

Top Level Entities

Former Member

Hi. It has been a number of years since I worked with Xilinx FPGAs, so I am used to getting a development board with an Altera part on it, and there has always been some simple example code to synthesize for getting the flow up and running. We were also able to re-use the top-level entity's port list for further development. That's what I'm really looking for.

I have searched this site and google for quite some time looking for something similar? Do these sorts of simple projects exist for the zed boards? I am starting development on the PicoZed 7030 SOM + Carrier, by the way.

Thanks,
Aric.

Parents Reply Children
  • 0 in reply to drozwood90

    That document is very helpful.

    I don't have a JTAG cable (yet), but I was able to hack the hello world example down to a simple loop that toggles a bit connected to an LED with a busy delay loop. I ripped out all the standard Xilinx startup code and libraries, and I used objcopy to produce an executable image from the elf file. It was 80 bytes of code.

    I loaded the bitstream with u-boot using tftp and the loadb u-boot command. Then I loaded the executable image with tftp and ran it with 'go ${loadaddr}'.

    Can't step through code that way, but at least I have something running.