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Hi. It has been a number of years since I worked with Xilinx FPGAs, so I am used to getting a development board with an Altera part on it, and there has always been some simple example code to synthesize for getting the flow up and running. We were also able to re-use the top-level entity's port list for further development. That's what I'm really looking for.

I have searched this site and google for quite some time looking for something similar? Do these sorts of simple projects exist for the zed boards? I am starting development on the PicoZed 7030 SOM + Carrier, by the way.

Thanks,
Aric.

0 drozwood90 over 10 years ago

Hi there,

We are currently working on getting a few reference designs out there. For the moment, if you take a look at the PicoZed documentation site:
http://picozed.org/support/documentation/4701

You can see the Board Definitions and Constraint files you can work with.

Please remember, using a PicoZed7030, ensure that you use the 1.8V selection (default) on the PZ-FMC-CC. The Zynq 7030 only supports 1.8V!

I would suggest you take one of our tutorials and walk through them substituting PicoZed7030 and related constraint files as you work through it.

As soon as we have reference designs together, they will be posted under the reference designs and tutorials section:
http://picozed.org/support/design/4736/71

As you work through your tutorial, if you have questions, let us know!

--Dan
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0 drozwood90 over 10 years ago

Hi there,

I wanted to let you know that we have posted some tutorials that can help get you up and running with this. You should be able to walk through the tutorial and create the solution file for the PZ7030. Then you will have a base project you can work with.
These have been created with Vivado 2015.1.
http://zedboard.org/support/design/4701/76

Take a look at Tutorial 2 or later.

--Dan
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0 Former Member over 10 years ago in reply to drozwood90

That document is very helpful.

I don't have a JTAG cable (yet), but I was able to hack the hello world example down to a simple loop that toggles a bit connected to an LED with a busy delay loop. I ripped out all the standard Xilinx startup code and libraries, and I used objcopy to produce an executable image from the elf file. It was 80 bytes of code.

I loaded the bitstream with u-boot using tftp and the loadb u-boot command. Then I loaded the executable image with tftp and ran it with 'go ${loadaddr}'.

Can't step through code that way, but at least I have something running.
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0 drozwood90 over 10 years ago

Aric,

Using TFTP was great thinking! I'm glad you got it working. For your information, I have used both the JTAG-HS2 and JTAG-HS3.
Here is a link to the HS3 cable:
http://avnetexpress.avnet.com/1/1/11833501-digilent-inc-jtag-hs3-programming-cable-xilinx-fpgas-210-299p-kit.html

--Dan
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