Hi. It has been a number of years since I worked with Xilinx FPGAs, so I am used to getting a development board with an Altera part on it, and there has always been some simple example code to synthesize for getting the flow up and running. We were also able to re-use the top-level entity's port list for further development. That's what I'm really looking for.
I have searched this site and google for quite some time looking for something similar? Do these sorts of simple projects exist for the zed boards? I am starting development on the PicoZed 7030 SOM + Carrier, by the way.
Thanks,
Aric.
