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microblaze on Zedboard

fayyazrafiq

I am facing problem to have microblaze on Zedboard alongwith ARM PS. I use the same design which was given on AR#50869(http://www.xilinx.com/support
/answers/50869.html#linkedARRecords)
and change the board specification in XPS Graphical view/import. Then I generate bit stream named system.bit. Then I follow the same procedure given in AR#50869 to download and create an image. I copy the image on the SD card (Boot.bin). I setup the jumpers on the ZedBoard for booting from SD card. Noting happenu2026 After that I open the XMD Console, I write on the command prompt
u201Cconnect mb mdmu201D. After that I got an error, no mdm found. Please help meu2026.
I shall very grateful for any help.
Fayyaz

  • 0

    Were you successful prior to this without MicroBlaze? What version of ISE tools are you using? If you're trying to duplicate what is posted in the AR, it would be easiest if you were using 14.2, same as the AR.

    Bryan

  • 0 in reply to bhfletcher

    Dear
    Thank you very much for your reply. I am using 14.3 version of Xilinx.  Actually, I successfully run the example for Zedboard. I tested software code for the example design for ARM and Microblaze. In addition, I successfully ported the freertos on ARM processor and tested. Now, I am trying to change the hardware design by using EMIO interface and try to connect the GPIO of PS to LD0(PL Side) on  the board. But I am having error
    ERROR:LIT:693 - Block 'MMCME2_ADV symbol
    "physical_group_clock_generator_0/clock_generator_0/SIG_MMCM1_CLKOUT0/clock_g

    enerator_0/clock_generator_0/MMCM1_INST/MMCM_ADV_inst"' has its target
       frequency, FVCO, out of range. Valid FVCO range varies depending on speed
       grade: 600MHz - 1200MHz(-1), 600MHz - 1440MHz(-2), 600MHz - 1600MHz(-3). The
       computed FCVO is a function of the input frequency CLKIN1_PERIOD, the
       division factor DIVCLK_DIVIDE, and the CLKFBOUT_MULT_F attribute (FVCO =
       1000*CLKFBOUT_MULT_F/(CLKIN1_PERIOD*DIVCLK_DIVIDE)). The CLKIN_PERIOD
       attribute may have been set by ngdbuild based on the user specified PERIOD
       constraint. The current calculated FVCO is 2400.000000 MHz.
    Errors found during logical drc.

    I try to check  the google, but could not succeed. Could you please help on that?

    Thanking you in anticipation.

  • 0

    Well, just looking at this error message, it is saying you tried to synthesize 2.4 GHz for FVCO on an MMCM, and that is not allowed. That doesn't seem to match with your statement regarding your changes related to enabling PS GPIO through the EMIO. Besides adding GPIO to EMIO, did you change anything else? If you can provide more details on what project you started with and what you changed, that will help us re-trace your steps.

    Bryan

  • 0 in reply to bhfletcher

    Dear
    Thank you again for the reply. Actually, I started with the project given with AR#50869 (http://www.xilinx.com/support/answers/50869.html). I only made connection for GPIO to EMIO. Actually, I solve the problem by changing the Clock_generator_0 input frequency to 100 MHz. Previously, it was 50 MHz. Now I have the same input (100 MHz) and output (100 MHz) frequency. I generate the bit stream, it is ok. I also tested the code on the arm processor. I am able to flash the LED0 on the ZedBoard. I observed a strange behaviour, the flashing of LED is very slow. Although, I set the blinking time to 1 tick interval.
    Could you please explain, is there anything wrong? Do, I need to change the Clock_Generator_0 setting to something else.

    Any help is highly appreciated.
    Thanks
    Fayyaz