PicoZed USB PHY always in RESET?

Question

We have an issue in which the USB PHY (USB3320) is always held in RESET. The attached picture describes the issue also.

The root cause is the following:

PS_MIO7 signal is 1.8V due Bank 501 being set to 1.8V.
TI AND gate IC SN74AUP2G08DQER is spec'd VIH = 2V min
Therefore the input to the AND logic can never = 1 (>2V).
Therefore the signal USB_OTG_RST_N.

This design is across the Rev A, C, and E schematics. How can we ensure that the USB3320 device is not in reset.

Thank you,

Adam

michaelkellett · Accepted Answer

I'm looking at a REVC schematic - the Ethernet reset is treated in a very similar way but there is a pull up resistor and a FET to make a rough and ready level shifter.

You could cut some track and insert a similar thing on the USB signal.

If you can't get at the tracks you could lift a pin on the USB3320 and connect it directly to 3.3V pin on the FPGA.

Or you could ask Avnet for your money back !

It's odd that other people haven't complained - maybe it usually works and they get away with it.

EEEK !

Just had a final look - MIO7 is Bank 500 which is 3.3V power so you are wrong in your diagnosis.

Your problem is elsewhere - try measuring some signals - you can just about probe the pins on U9 and U10.

MK

jafoste4 · Answer

Hi Adam,

Refering to the schematic for the PicoZed 7010/7020 or PicoZed 7015/7030 SOM, PS_MIO7 is tied to Bank 500.

3005.contentimage_189921.png

and bank 500 is driven to 3.3V.

3821.contentimage_189922.png

let me know if you need any further explanation.

Thanks!

Josh

PicoZed USB PHY always in RESET?

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