Hello.
I have just designed a carrier board for a PicoZed 7015/7030. I have verified all power and boot up, and it works, now I want to use the FPGA and the IOs.
I have been able to access the IOs of bank 34/35, and this works fine. I have also been able to use the MIO pins. But I have an issue when it comes to the IO pins of Bank 13. I have not been able to use those yet. I have tried connecting them diretly to PL like I did with bank 34/35, e.g. by setting a counter in PL and connecting IO's directly to the output of the counter. I have also tried accessing this from PS via EMIO. But I cannot seem to get these pins to change...
Is there any setting in Vivado that needs to be set? When I tried EMIO i enable EMIO and used a constraint file to set the pins. When I tried directly form PL I used the same method that worked for bank 34/35, and this is to set the IOs via contraint file. I have only tried these as outputs yet.
Any tips?
