Can I use AFE7444EVM (JESD204B) with PicoZed FMC Carrier V2?

Question

Hi,

I am currently developing a new application where I need to measure the FFT of three signals that contain multiple frequency components (between 50 and 400 MHz). My initial plan was to use an ADC evaluation module from Texas Instruments (AFE7444EVM), together with the 7015 PicoZed and the PicoZed FMC Carrier Card V2 (I would rather not develop a carrier card myself).

I have three questions about this implementation:

1- Can I directly connect the FMC connectro from AFE7444EVM to the PicoZed Carrier card (i.e., is the PicoZed FMC Carrier Card compatible with the JESD204B IP)?

2- Can I do the FFT analysis directly in the PicoZed or should I transfer the data to a PC? What do you think would be the faster option (I only need the AC power and phase of specific frequencies)?

3- Is the 7015 PicoZed fast enough for my application? Or should I use another board?

PS1: If you need any extra information about my system design, please let me know.

PS2: I am very new to FPGA development, so detailed answers or any good references are very welcomed.

mbrown · Accepted Answer

One thing that everyone finds challenging is Implementing the JESD204B protocol. Xilinx offers a pay-for IP core ( link ), but implementing it in a system takes some expertise. You might want to consider using the Xilinx ZCU111 evalution board , which has their UltraScale+ RFSoC device. You can do 8 channels 12-bit ADC @ 4Gsps and 8 channels 14-bit DAC at 6.544Gsps (instantaneous analog BW for both is 4GHz). The advantage there is that the converters hook natively into the programmable logic - no JESD204B mess. You'll probably want to add this SMA daughtercard as well. Depending on your timeline, you may want to either hire a consultant or sign up for training. Honestly, people make a living knowing how to connect gigasample converters to FPGAs and do all the high-speed signal processing on the back end. Beyond HDL knowledge, you'll need experience in making tradeoffs between resource utilization vs. speed, closing timing, debugging algorithms, improving throughput, the list goes on. Best of luck. Sounds like a very interesting project! /Matt