Hi all,
I was alerted by Xilinx's Design Advisory e-mails about a change to the behavior of the WDQS Control for DDR4.
This seems specific to LPDDR4 as it was a change in JEDEC LPDDR4, specifically JESD209-4B.
Essentially, if you are using the 2019.2 version of Xilinx tools, you do not have to worry about this. If you are using a previous design tool, it is recommended to add this command into your Vivado design flow:
set_property CONFIG.PSU__DDRC__VENDOR_PART HYNIX [get_bd_cells /zynq_ultra_ps_e_0]
If you are using older tools, and one of our products with LPDDR4, you will want to check out this Answer Record.
https://www.xilinx.com/support/answers/72499.html
Here is a non-exhaustive list of products that had LPDDR4 designed into it:
- Ultra96V1
- Ultra96V2
UltraZed-EG and UltraZed-EV use DDR4, instead of LPDDR4.
What version of tools are you using? Have you updated to 2019.2? Are you using Vitis?
If you are using an older tool, what is the reason for not updating tools?
Leave your comments below!
--Dan
