Hi,
I've downloaded the UltraZed-Ev platform file from here:
http://zedboard.org/support/design/25481/161
and I ran a synthesis with SDAccel 2019.1 on one of the Xilinx SDAccel example design and I faced the following issue:
WARNING: [Vivado 12-508] No pins matched '/zynq_ultra_ps_e_0_pl_clk0'.
INFO: [Timing 38-35] Done setting XDC timing constraints.
WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_pins /zynq_ultra_ps_e_0_pl_clk0]'.
Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks.
ERROR: [runtcl-1] ERROR: [Common 17-55] 'get_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
ERROR: [Common 17-39] 'send_msg_id' failed due to earlier errors.
Is there an issue with the UltraZed-EV platform file?
I've also tested with the Vitis 2020.1 and got the exact same issue
Regards
