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Avnet Boards General ultra zed  7EV som board
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  • zedboardcmty
Related

ultra zed  7EV som board

akshayhublikar
akshayhublikar over 4 years ago

Hi

 

I have designed a carrier board for ultrazed 7EV SOM module

 

I am using GT lanes as below

 

Lane 0  --  SATA0

Lane 1 -  SATA1

Lane 2 --- USB3.0

Lane3 --  Display port

 

Lane 0 sata drive, Lane 2  usb and Lane 3  display port  are working fine.  Only Lane 1 sata drive always shows link down.

 

Checked continuity of traces , routing  , power , all looks fine.  Any hint on why Lane1 sata drive always shows link down ???????????

 

 

Regards

Akshay

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  • narrucmot
    0 narrucmot over 4 years ago

    Hi Akshay,

     

    Our resident GT expert is on vacation until January, but I will attempt to help you here.  I would first suggest examining the SATA peripheral and clocking settings in the Zynq MPSoC PS configuration and compare them to a known-good Vivado hw project for this SOM.  Such a project can be found included in the PetaLinux BSP that you can download here:
    UltraZed-EV -> Reference Designs -> PetaLinux Board Support Packages

     

    Xilinx UG1144 explains how to "install" (extract) the BSP.

    https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug1144-petalinux-tools-reference-guide.pdf

    $ petalinux-create -t project -s /path/to/<filename.bsp>

     

    --Tom

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  • akshayhublikar
    0 akshayhublikar over 4 years ago in reply to narrucmot

    Hi Tom

     

    Thanks for quick reply.

     

    I have tried all things you have suggested. But no luck.

     

    I just wanted to know if we can run some loopback tests or any other tests to check if TX and RX lines are working or not.

     

    Also is there any standalone or bare metal application to test sata ? Since Sata on lane 0 works , not sure what is missing on lane 1 due to which sata always shows link down.

     

    Regards

    Akshay

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  • akshayhublikar
    0 akshayhublikar over 4 years ago in reply to narrucmot

    Hi Tom

     

    Thanks for quick reply.

     

    I have tried all things you have suggested. But no luck.

     

    I just wanted to know if we can run some loopback tests or any other tests to check if TX and RX lines are working or not.

     

    Also is there any standalone or bare metal application to test sata ? Since Sata on lane 0 works , not sure what is missing on lane 1 due to which sata always shows link down.

     

    Regards

    Akshay

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  • drozwood90
    0 drozwood90 over 4 years ago in reply to akshayhublikar

    Hi there,

     

    I've not done this in a long while (2018.2), but back then, you could run IBERT on the GTRs.  I suspect that, with a loopback adapter is what you are looking for.

    UG936 chapter 10 (page 175 - 211)

    https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug936-vivado-tutorial-programming-debugging.pdf

     

    I did not look to see if that was updated for newer tools, but the steps should be the same.  From this standpoint, I do not think that Vivado has changed much, if at all.

    Worst case, you can still download the older tools for use with the above instruction.

     

    I also do not mean to be insulting, but also, please double check that you have all your GTRs setup properly.  You seem to have listed that you checked everything else!  I believe you do, but let's be certain!

    Here is my suggestion for what I believe should be correct based on what you wrote.

    0181.contentimage_193359.png

    Lastly, if you see that IBERT is fine, as Tom mentioned, please check that the OS has all the proper links, configurations, device tree entries, etc.  If the XSA / HDF is configured properly, but the OS is not also keyed to the same resources, the proper links will not be made within the OS and it will erroneously state that you do not have link.

     

    --Dan

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