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ZedBoard Pmod Headers Not Working

oshears

Hi All,

 

I am working with a ZedBoard trying to test the output functionality of the Pmod headers. The Pmod headers on this ZedBoard have worked in the past, however, when I try to work with them now it appears that they do not transmit any output data. I've tried this for all four programmable logic accessible headers (JA1, JB1, JC1, JD1). When I assign the output to the LEDs I am able to see the output successfully, but it does not come through the Pmod headers.

 

Here is a very simple HDL file and constraints file that I'm using on my ZedBoard that should produce output on the Pmod headers.

 

HDL File (dut.v):

`timescale 1ns / 1ps

module dut(

    output PMOD

    );

    assign PMOD = 1;

endmodule

Constraints File Contents (constraints.xdc):

# ----------------------------------------------------------------------------

# JA Pmod - Bank 13

# ----------------------------------------------------------------------------

set_property PACKAGE_PIN Y11  [get_ports {PMOD}];  # "JA1"

set_property PACKAGE_PIN AA8  [get_ports {PMOD}];  # "JA10"

set_property PACKAGE_PIN AA11 [get_ports {PMOD}];  # "JA2"

set_property PACKAGE_PIN Y10  [get_ports {PMOD}];  # "JA3"

set_property PACKAGE_PIN AA9  [get_ports {PMOD}];  # "JA4"

set_property PACKAGE_PIN AB11 [get_ports {PMOD}];  # "JA7"

set_property PACKAGE_PIN AB10 [get_ports {PMOD}];  # "JA8"

set_property PACKAGE_PIN AB9  [get_ports {PMOD}];  # "JA9"

# ----------------------------------------------------------------------------

# JB Pmod - Bank 13

# ----------------------------------------------------------------------------

set_property PACKAGE_PIN W12 [get_ports {PMOD}];  # "JB1"

set_property PACKAGE_PIN W11 [get_ports {PMOD}];  # "JB2"

set_property PACKAGE_PIN V10 [get_ports {PMOD}];  # "JB3"

set_property PACKAGE_PIN W8 [get_ports {PMOD}];  # "JB4"

set_property PACKAGE_PIN V12 [get_ports {PMOD}];  # "JB7"

set_property PACKAGE_PIN W10 [get_ports {PMOD}];  # "JB8"

set_property PACKAGE_PIN V9 [get_ports {PMOD}];  # "JB9"

set_property PACKAGE_PIN V8 [get_ports {PMOD}];  # "JB10"

# Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard.

set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]];

 

Has anyone experienced this faulty behavior? Are they any workarounds or solutions?

  • 0

    HI there,

     

    Did you set your direction?  You likely have a warning or critical warning telling you something around your IO constrainting.

     

    --Dan

  • 0 in reply to drozwood90

    Hi there,

     

    I would suggest you get a project example and take a look at that - compare that to what you have and see what is missing.

     

    --Dan

  • 0 in reply to drozwood90

    Is it possible to specify the direction more than what has already been done in the HDL file above? In the code I have designated that the PMOD is an output.

  • 0 in reply to oshears

    Hi there,

     

    You will need to look into the logs to see if the tool is having issues.  You don't have to specify direction.  However, I don't know what you have in your design, BD, rest of your constraints, clocks, etc.  XDC is follows the SDC standards, and whatever is the last thing is what is accepted as true.

     

    I'm also not 100% familiar with Verilog, and in VHDL what you wrote probably wouldn't do anything.  I am not sure if an integer is going to be able to be interpreted to a BUS.  Also the way you defined PMOD is not a BUS, so again, I am not sure what you are trying to define.

     

    --Dan

  • 0 in reply to drozwood90

    Thanks for your response Daniel. There are not any issues that I can see in the log files for Vivado. The code that I've posted is just a simple example to provide a logic-1 (high) on the Pmod outputs. In this Verilog example the integer 1 would be interpreted as logic-1. Here I just want to display this single high bit on all of the JA1 and JB1 Pmod outputs.

  • 0 in reply to oshears

    HI there,

     

    No problem, thank you for explaining and being clear.  That is helpful.  To also try to be clear, I understand what you were trying to do with Verilog.  I have written it and can read it.  What I meant was, I am not familiar enough with writing Verilog, that if there is some syntactical thing, I cannot say what the language is doing.  In VHDL, what you wrote in the way you did, it would error out due to the strong typing of the language and a bit vs bus definition.  I think you will agree that a BIT is not the same as a number.  In that case, what you wrote as assigning a 1, likely is not working as you expect as you likely need to define ALL pins as 1, so more like a HEX representation: 0xFFFF

     

    What I stated about the outputs, is still true.  I said that XDC interprets "last defined" as the correct thing you wanted.  That is still true and why there are no constraint errors.  It's not wrong.  However it is not what you described that you want.  As I said, I do not think that you defined a bus.  You defined 1 pin V8 as the "object" PMOD.  If you are not seeing any errors anywhere else, I assume if you monitor that one pin, it will be toggling as you toggle it in the code as that is what I read as the behavior of what you provided.  So it is not a faulty behavior in my mind.  It is doing exactly what it is supposed to.

     

    If what you wrote was VHDL, you would likely have seen that is not a bus.  It would have complained as it wouldn't know how to place 1 bit into a bus.  On the other hand, depending on how '1' is defined, you may have not seen the error, however you would have been forced into assigning logic 1 as a BIT into what you think is a bus.  Thus still showing you where the problem is...just from another side.

     

    https://github.com/Avnet/hdl/blob/2020.2/boards/uz7ev_evcc/base/uz7ev_evcc_factest.xdc#L70

     

    Example of a BUS definition.

     

    --Dan

  • 0 in reply to drozwood90

    Thanks for the explanation Dan. I made some tweaks to my Verilog code to define PMOD as a bus (i.e., output [7:0] PMOD). It appears that the issue was as you said: I was attempting to assign one output to several FPGA pins, however, the actual implementation ended up using the last constraint I specified as the output pin (V8) (I can see this when I look at the package view in the Implemented Design section of Vivado).

     

    This is very strange because when I try this experiment again with LEDs I am able to see all of the LEDs light up with only the single output port "PMOD". I wonder why it can produce the output on all of the LEDs but not all of the PMODs for one output port.

  • 0 in reply to oshears

    Hi there,

     

    Look at the XDC around the LEDS.  I would think there's a reason based on that.

    Also, to point something else out, the timescale you have listed means nothing to the FPGA - if you are intending on that telling the implementation or PAR (place and route) something.

    I also hope that you have timing constraints in there somewhere.  You might want to look at Xilinx's user guide on XDC and take some training courses on setting up XDC files.

     

    Note, that in the future, you might get better assistance from the Digilent forum on the ZedBoard.  We really only work with DBA (Designed By Avnet) products here.

     

    I am glad you got it working!

     

    --Dan